Abstract: A semiconductor structure and a method for fabricating it are disclosed. In the semiconductor structure, a heat-equalizing layer is arranged between stacked first and second substrates and includes a heat-dissipating material film, which can promote horizontal transfer of heat produced in the semiconductor structure between the first and second substrates.

Abstract: A semiconductor device and a method for fabricating it are disclosed. In the method, second and first substrates are bonded to obtain increased operating efficiency. Moreover, a heat dissipation unit, which includes a heat-dissipating semiconductor layer and a first heat-dissipating metal channel extending through the heat-dissipating semiconductor layer and dielectric layers on a surface thereof, is bonded to a surface of the first substrate to accelerate dissipation of heat generated during operation of the second and first substrates, imparting improved heat dissipation capacities to the semiconductor device.

Abstract: The present invention provides a semiconductor device and a method of fabricating the device, in which in each adjacent pair of semiconductor substrates, a first semiconductor substrate is bonded to a backside of a second semiconductor substrate, and external connection terminals are adjacent, and electrically connected, to a second semiconductor substrate. In each adjacent pair of semiconductor substrates, there is a first dielectric layer containing plug structures, which electrically connect the semiconductor substrates to each other. With this arrangement, power from an external power source can be supplied to each semiconductor substrate through a power transmission path constructed of plug structures. At least some first dielectric layers each contain a DTC structure, which is electrically connected to second ends of the plug structures in specific first dielectric layer.

Abstract: The present invention relates to a TSV electrical interconnect structure having a high aspect ratio and method of manufacturing it. In the method, a backside via and a backside contact pad connected to the backside via are formed on a backside of the semiconductor base. A front-side via connected to the backside via is then formed in the front side of the semiconductor base, obtaining a TSV which electrically connects the front side and backside of the semiconductor base that has a thickness greater than or equal to 150 ?m. The TSV has an aspect ratio higher than 20, which can meet the requirements of package-level matching. The TSV electrical interconnect structure having a high aspect ratio can be connected to a package substrate or a PCB board through the backside contact pad. A rewiring layer on the front side of the semiconductor base is connected to the front-side via, and the TSV electrical interconnect structure having a high aspect ratio can provide an interconnection through the rewiring layer.

Abstract: A semiconductor device and a method for making it are disclosed. The semiconductor device includes a first substrate having a front side and a backside opposite thereto, wherein a device structure is formed at the front side of the first substrate, and a DTC is formed at the backside of the first substrate; a first insulating layer and a second insulating layer, which are formed on the front side and the backside of the first substrate, respectively; a first interconnect structure and a second interconnect structure, the first interconnect structure formed in the first insulating layer, the second interconnect structure formed in the second insulating layer; and a plug structure formed in the first insulating layer, one end of the plug structure electrically connected to the device structure through the first interconnect structure, the other end of the plug structure electrically connected to the DTC through the second interconnect structure.

Abstract: A semiconductor device includes a first wafer; a trench isolation ring formed in the first wafer and comprising a first metal layer; a first insulating dielectric layer formed on a surface of the first wafer, including at least one first through hole and at least one second through hole formed therein, the first through hole exposing a surface of the first metal layer, the second through hole exposing the surface of the first wafer; a barrier layer formed at least on the surface of the first wafer exposed in the second through hole; and a second metal layer formed on the first insulating dielectric layer so as to fill up the first and second through holes. The semiconductor device circumvent increased contact resistance, possible aluminum spiking and other problems. The method exhibits improved robustness and imparts higher performance to a semiconductor device fabricated using the method.

Abstract: A method of design for matching of wafers, a wafer bonding structure and a chip bonding structure includes: providing a first wafer including unit arrays that each include at least two first dies; providing a second wafer including second dies that each cover at least one of the unit arrays, and the second dies matched in terms of performance with the first dies in the unit arrays that it covers. The first and second wafers are provided with corresponding alignment marks. With this application, two or more wafers with corresponding dies differing considerably in terms of shape or area can be designed to match each other and become suitable to be bonded together. This enables effective area utilization of, and better matching in terms of area and performance between, the dies, greatly shortens the development time of new products and adds great diversity and freedom to product design.

Abstract: A semiconductor device and a method for manufacturing the same. When a pattern for etching is formed through photolithography after forming a photoresist layer on an adhesion layer, a sub-resolution auxiliary pattern of the mask is above the non-lead-out region, and an exposable pattern of the mask is above a lead-out region. In the photolithography, a first partial exposure region exposed partially in depth is formed in the photoresist layer corresponding to the sub-resolution auxiliary pattern, and an exposed pattern that is exposed completely is formed in the photoresist layer corresponding to the exposable pattern. After anisotropic etching on the adhesion layer through the photoresist layer, both an opening running through a partial thickness of the adhesion layer and a via hole running through the adhesion layer are formed. The opening balances a load in planarization during a process of filling the via hole.

Abstract: A semiconductor device and a method for manufacturing the same. When a pattern for etching is formed through photolithography after forming a photoresist layer on an adhesion layer, a sub-resolution auxiliary pattern of the mask is above the non-lead-out region, and an exposable pattern of the mask is above a lead-out region. In the photolithography, a first partial exposure region exposed partially in depth is formed in the photoresist layer corresponding to the sub-resolution auxiliary pattern, and an exposed pattern that is exposed completely is formed in the photoresist layer corresponding to the exposable pattern. After anisotropic etching on the adhesion layer through the photoresist layer, both an opening running through a partial thickness of the adhesion layer and a via hole running through the adhesion layer are formed. The opening balances a load in planarization during a process of filling the via hole.