Patents by Inventor Bei Chao Zhang
Bei Chao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9490165Abstract: Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.Type: GrantFiled: December 30, 2010Date of Patent: November 8, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Luying Du, Fan Zhang, Jun Chen, Bei Chao Zhang, Juan Boon Tan
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Patent number: 9147654Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.Type: GrantFiled: July 7, 2008Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn
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Patent number: 8519445Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.Type: GrantFiled: July 14, 2011Date of Patent: August 27, 2013Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
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Patent number: 8358007Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.Type: GrantFiled: June 8, 2010Date of Patent: January 22, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang, Luying Du, Wei Liu, Yeow Kheng Lim
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Publication number: 20120255586Abstract: An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.Type: ApplicationFiled: April 11, 2012Publication date: October 11, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Boon Meng SEAH, Bei Chao ZHANG, Raymond JOY, Shao Beng LAW, John SUDIJONO, Liang Choo HSIA
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Publication number: 20120168915Abstract: Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Luying DU, Fan ZHANG, Jun CHEN, Bei Chao ZHANG, Juan Boon TAN
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Patent number: 8177993Abstract: An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.Type: GrantFiled: November 5, 2006Date of Patent: May 15, 2012Assignee: GLOBALFOUNDRIES Singapore Pte LtdInventors: Boon Meng Seah, Bei Chao Zhang, Raymond Joy, Shao Beng Law, John Sudijono, Liang Choo Hsia
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Patent number: 8115276Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.Type: GrantFiled: June 3, 2008Date of Patent: February 14, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shaoqing Zhang, Fan Zhang, Shao-fu Sanford Chu, Bei Chao Zhang
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Patent number: 8102054Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 23, 2010Date of Patent: January 24, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Publication number: 20110266628Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.Type: ApplicationFiled: July 14, 2011Publication date: November 3, 2011Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Vincent HO, Wenhe LIN, Young Way TEH, Yong Kong SIEW, Bei Chao ZHANG, Fan ZHANG, Haifeng SHENG, Juan Boon TAN
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Patent number: 7993997Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.Type: GrantFiled: October 1, 2007Date of Patent: August 9, 2011Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
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Patent number: 7947604Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.Type: GrantFiled: January 25, 2008Date of Patent: May 24, 2011Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Fan Zhang, Lup San Leong, Yong Kong Siew, Bei Chao Zhang
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Publication number: 20100314774Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: ApplicationFiled: August 23, 2010Publication date: December 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
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Publication number: 20100314763Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.Type: ApplicationFiled: June 8, 2010Publication date: December 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang, Luying Du, Wei Liu, Yeow Kheng Lim
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Patent number: 7803704Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 22, 2008Date of Patent: September 28, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Patent number: 7781895Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: June 17, 2009Date of Patent: August 24, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 7691739Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.Type: GrantFiled: March 13, 2006Date of Patent: April 6, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
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Patent number: 7678586Abstract: An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.Type: GrantFiled: December 8, 2005Date of Patent: March 16, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Huang Liu, Bei Chao Zhang, Wuping Liu, John Leonard Sudijono, Liang Choo Hsia
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Publication number: 20100044869Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
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Publication number: 20100001370Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.Type: ApplicationFiled: July 7, 2008Publication date: January 7, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn