Patents by Inventor Bejoy G. Oomman

Bejoy G. Oomman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Design-for-Test Techniques for a Digital Electronic Circuit
    Publication number: 20170205464
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Application
    Filed: March 9, 2017
    Publication date: July 20, 2017
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne
  • Design-for-test techniques for a digital electronic circuit
    Patent number: 9651615
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 16, 2017
    Assignee: Genesys Testware, Inc.
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne
  • Design-for-Test Techniques for a Digital Electronic Circuit
    Publication number: 20160320452
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 3, 2016
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne
  • Design-for-test techniques for a digital electronic circuit
    Patent number: 9423455
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 23, 2016
    Assignee: Genesys Testware, Inc.
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne
  • Design-for-Test Techniques for a Digital Electronic Circuit
    Publication number: 20160169971
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne