Patents by Inventor Belford T. Coursey
Belford T. Coursey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9331236Abstract: Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate.Type: GrantFiled: September 25, 2015Date of Patent: May 3, 2016Assignee: Micron Technology, Inc.Inventors: Belford T. Coursey, F. Daniel Gealy, George E. Beck
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Publication number: 20160027863Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.Type: ApplicationFiled: July 2, 2015Publication date: January 28, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett W. Busch, Mingtao Li, Lequn Jennifer Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
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Publication number: 20160013360Abstract: Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate.Type: ApplicationFiled: September 25, 2015Publication date: January 14, 2016Inventors: Belford T. Coursey, F. Daniel Gealy, George E. Beck
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Patent number: 9147803Abstract: Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate.Type: GrantFiled: January 2, 2013Date of Patent: September 29, 2015Assignee: Micron Technology, Inc.Inventors: Belford T. Coursey, F. Daniel Gealy, George E. Beck
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Patent number: 9076680Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.Type: GrantFiled: October 18, 2011Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, Mingtao Li, Jennifer Lequn Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
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Publication number: 20140183443Abstract: Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Belford T. Coursey, F. Daniel Gealy, George E. Beck
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Publication number: 20130093050Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett W. Busch, Mingtao Li, Jennifer Lequn Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
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Patent number: 7355231Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.Type: GrantFiled: March 28, 2005Date of Patent: April 8, 2008Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey
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Patent number: 7211855Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.Type: GrantFiled: April 25, 2006Date of Patent: May 1, 2007Assignee: Micron Technology, Inc.Inventors: Belford T. Coursey, Brent D. Gilgen
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Patent number: 7148536Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.Type: GrantFiled: December 8, 2003Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey
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Patent number: 7115970Abstract: Capacitors for use in an integrated circuit are provided. One aspect of this disclosure relates to a method of making a capacitor. According to various embodiments of the method a bottom electrode adapted to act as an etch stop is formed, a substantially cone-shaped first plate of conductive material is formed having an interior and exterior surface and terminating at the bottom electrode, a layer of dielectric material is formed on at least a portion of the interior and exterior surface of the first plate and substantially conforming to the shape of the first plate, and a second plate of conductive material is formed over the layer of dielectric material. Other aspects and embodiments are provided herein.Type: GrantFiled: September 1, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventors: Brent Gilgen, Belford T. Coursey
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Patent number: 7105884Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.Type: GrantFiled: March 15, 2001Date of Patent: September 12, 2006Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey
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Patent number: 7087949Abstract: A method used to form a semiconductor device comprises forming a layer such as a container capacitor layer having a bottom plate layer. The bottom plate layer is formed to define a receptacle, and a rim which defines an opening to an interior of the receptacle. The bottom plate layer is formed to have a smooth texture. Subsequently, an inhibitor layer is formed on the rim of the bottom plate layer while a majority of the receptacle defined by the bottom plate layer remains free from the inhibitor. With the inhibitor layer on the rim of the bottom plate layer, at least a portion of the receptacle is converted to have a rough texture, such as to hemispherical silicon grain (HSG) polysilicon, while subsequent to the conversion the smooth texture of the rim which defines the opening to the interior of the receptacle remains. A resulting structure is also described.Type: GrantFiled: September 8, 2003Date of Patent: August 8, 2006Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey
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Patent number: 7078760Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.Type: GrantFiled: October 22, 2004Date of Patent: July 18, 2006Assignee: Micron Technology, Inc.Inventors: Belford T. Coursey, Brent D. Gilgen
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Patent number: 7026678Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.Type: GrantFiled: January 6, 2003Date of Patent: April 11, 2006Assignee: Micron Technoloy, Inc.Inventor: Belford T. Coursey
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Patent number: 6974993Abstract: A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.Type: GrantFiled: September 13, 2004Date of Patent: December 13, 2005Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey
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Patent number: 6893958Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.Type: GrantFiled: April 26, 2002Date of Patent: May 17, 2005Assignee: Micron Technology, Inc.Inventors: Belford T. Coursey, Brent D. Gilgen
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Patent number: 6888217Abstract: A capacitor including a first plate of conductive material that is formed in a predetermined shape. A layer of dielectric material is formed on at least a portion of the first plate and substantially conforms to the predetermined shape of the first plate. A second plate of conductive material is formed over the layer of dielectric material.Type: GrantFiled: August 30, 2001Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Brent Gilgen, Belford T. Coursey
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Patent number: 6830972Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.Type: GrantFiled: September 10, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey
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Patent number: 6790725Abstract: A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.Type: GrantFiled: May 17, 2002Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventor: Belford T. Coursey