Patents by Inventor Belkacem Derras
Belkacem Derras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10148470Abstract: A method includes receiving a data signal over a multi-input multi-output (MIMO) channel. The method further includes equalizing the data signal, by an adaptive equalizer circuit having an associated target, to provide an equalized output of the data signal. As part of the method, taps of the equalizer circuit and coefficients of the target are estimated. A constraint is imposed on the coefficients of the target as part of the estimation of the coefficients of the target. A similar minimization process is used with constraint imposed on whitening filter taps associated with a DDNP detector in the MIMO channel.Type: GrantFiled: August 11, 2017Date of Patent: December 4, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Belkacem Derras, Raman Venkataramani, William M. Radich
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Patent number: 10069653Abstract: An equalizer and an equalization method. The method includes receiving a data signal over a channel. The method further includes equalizing the data signal, by a blind partial response equalizer circuit, to provide an equalized output of the data signal. An estimation of partial response equalizer taps employed to determine the equalized output, by the blind partial response equalizer circuit, is carried out independently of true channel input symbols and detected symbols corresponding to the data signal.Type: GrantFiled: May 12, 2017Date of Patent: September 4, 2018Assignee: SEAGATE TECHNOLOGY LLCInventor: Belkacem Derras
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Patent number: 9985775Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.Type: GrantFiled: December 6, 2016Date of Patent: May 29, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Ara Patapoutian, Belkacem Derras, William Michael Radich, Michael J. Link, Bruce D. Buch
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Patent number: 9973354Abstract: In certain embodiments, an apparatus may comprise a circuit configured to receive a plurality of samples of an input signal. The circuit may update one or more equalizer parameters using partial zero forcing equalization. Further, the circuit may generate an equalized signal based on the plurality of samples of the input signal and the one or more equalizer parameters.Type: GrantFiled: June 25, 2016Date of Patent: May 15, 2018Assignee: Seagate Technology LLCInventors: William Michael Radich, Raman Venkataramani, Belkacem Derras, Rishi Ahuja
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Patent number: 9947362Abstract: A system may include an interpolator circuit configured to receive a first signal with a first rate and to generate an interpolated signal with a second rate. The system may include a cancellation circuit configured to determine an interference component signal based on the interpolated signal. The system may further comprise an adder configured to receive a second signal with the second rate and to cancel interference in the second signal using the interference component signal to generate a cleaned signal.Type: GrantFiled: June 25, 2016Date of Patent: April 17, 2018Assignee: Seagate Technology LLCInventors: Raman Venkataramani, Belkacem Derras, William Michael Radich
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Patent number: 9654145Abstract: A storage device disclosed herein includes a memory and a write channel configured to interleave a plurality of code-words to generate a plurality of multiplet sequences such that at least two of the plurality of code-words interleave to the end of the interleaving process. In one example implementation, for each of the multiplet sequences no two successive multiplets are from the same code-word, a multiplet including a plurality of bits from a single code-word.Type: GrantFiled: November 24, 2014Date of Patent: May 16, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Belkacem Derras, Deepak Sridhara, Richard Parshall
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Patent number: 9613652Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.Type: GrantFiled: July 24, 2015Date of Patent: April 4, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Michael J. Link, Bruce Douglas Buch, Belkacem Derras
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Publication number: 20170085364Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Ara Patapoutian, Belkacem Derras, William Michael Radich, Michael J. Link, Bruce D. Buch
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Patent number: 9590803Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.Type: GrantFiled: May 22, 2015Date of Patent: March 7, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Belkacem Derras, Raman Venkataramani, William Michael Radich
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Publication number: 20170025147Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.Type: ApplicationFiled: July 24, 2015Publication date: January 26, 2017Inventors: Michael J. Link, Bruce Douglas Buch, Belkacem Derras
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Patent number: 9525576Abstract: A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.Type: GrantFiled: July 24, 2015Date of Patent: December 20, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Ara Patapoutian, Belkacem Derras, William Michael Radich, Michael J. Link, Bruce Douglas Buch
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Publication number: 20160344540Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.Type: ApplicationFiled: May 22, 2015Publication date: November 24, 2016Inventors: Belkacem Derras, Raman Venkataramani, William Michael Radich
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Patent number: 9407472Abstract: Multiple input single output (MISO) systems and processes are presented that can adaptively equalize multiple signals to produce an output. In some examples, the MISO systems can include a fast transversal recursive least square (RLS) algorithm to produce the output. Fast transversal RLS algorithms can be less complex than other RLS algorithms. In some examples, the fast transversal RLS algorithm may be optimized to have no division operations. The MISO system may have two or more inputs.Type: GrantFiled: June 18, 2014Date of Patent: August 2, 2016Assignee: Seagate Technology LLCInventors: Belkacem Derras, William Michael Radich, Rishi Ahuja
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Patent number: 9093115Abstract: A system can include a first buffer storing a first fragment of data for a first data sector in a first track of a storage medium, a second buffer storing a second fragment of data for a second data sector in a second track of the storage medium adjacent to the first track, a processor configured to determine an estimated region of overlap between the first data fragment and the second data fragment, and a circuit configured to refine the estimated region of overlap by determining an offset value to offset an estimated beginning portion of overlap by the second fragment.Type: GrantFiled: August 28, 2014Date of Patent: July 28, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Kendall Hayne Fung, David H. Dahlem, Jr., Raman Chatapuram Vankataramani, Belkacem Derras, William Michael Radich
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Patent number: 8296638Abstract: A Viterbi detector includes a plurality of possible bit patterns that correspond to branches of a detector trellis and a plurality of data dependent noise prediction filters, with multiple filters of different orders being associated with a given bit pattern. A method of decoding includes applying observables to a Viterbi detector that associates a plurality of data dependent noise filters with a given possible bit pattern that corresponds to a branch of the detector trellis, calculating the composite maximum likelihood branch metric by incorporating the results of filtering the observables through the associated plurality of filters, calculating the composite maximum likelihood branch metrics in the same manner for other possible bit patterns, and so forth, and associating soft output values with detected bits in the observables based on the calculated branch metrics.Type: GrantFiled: May 4, 2009Date of Patent: October 23, 2012Assignee: Seagate Technology LLCInventor: Belkacem Derras
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Publication number: 20100281347Abstract: A Viterbi detector includes a plurality of possible bit patterns that correspond to branches of a detector trellis and a plurality of data dependent noise prediction filters, with multiple filters of different orders being associated with a given bit pattern. A method of decoding includes applying observables to a Viterbi detector that associates a plurality of data dependent noise filters with a given possible bit pattern that corresponds to a branch of the detector trellis, calculating the composite maximum likelihood branch metric by incorporating the results of filtering the observables through the associated plurality of filters, calculating the composite maximum likelihood branch metrics in the same manner for other possible bit patterns, and so forth, and associating soft output values with detected bits in the observables based on the calculated branch metrics.Type: ApplicationFiled: May 4, 2009Publication date: November 4, 2010Inventor: Belkacem Derras