Abstract: The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.

Abstract: The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.

Abstract: A method and system for employing systematic check codes for detecting a predetermined number of unidirectional errors in the transmission of data. In accordance with the invention check codes are produced from information codes such that for all possible pairs of (n+m)-bit data words formed by a predetermined set of n-bit information codes and corresponding m-bit check codes, either the pair of words is unordered or the Hamming distance between the data words of the pair is greater than or equal to t+1, where t is the maximum number of unidirectional errors that can be detected. First check codes are generated at a data source, second check codes are generated from the received information code at a data sink, and the received first check codes are compared with the second check codes to determine the existence of a disparity. Sequential and combinational logic circuits are provided for producing check codes having two or more bits.