Abstract: The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.

Abstract: The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.

Abstract: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided.

Abstract: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided.

Abstract: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided.

Abstract: A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a method according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a a method allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a methodology according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance . In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a method allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a methodology according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a methodology according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.