Patents by Inventor Ben Han

Ben Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11999954
    Abstract: Disclosed herein are programmable, conditionally activated small interfering RNA constructs (Cond-siRNAs) and methods of making and using the same as therapeutic agents. The Cond-siRNA comprises a sensor strand, a core strand, and a guide strand, which crossover to form a sensor duplex and a RNAi duplex attached to each other to form a single structure. Upon binding an input strand to the sensor strand, the Cond-siRNA is activated and releases RNAi targeting a desired gene.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 4, 2024
    Assignees: Clty of Hope, California Institute of Technology
    Inventors: Si-ping Han, William A. Goddard, III, Marwa Ben Haj Salah, Lisa Scherer, John J. Rossi
  • Patent number: 11973889
    Abstract: The present disclosure relates to a searchable encrypted data sharing method and system based on blockchain and homomorphic encryption, which protects security of sensitive data on the blockchain and realizes searchable and homomorphic calculation of data ciphertext. According to the present disclosure, a data owner encrypts the generated sensitive data and the keywords extracted according to the data with his own key, and then sends the encrypted transaction information to the cloud server. The cloud server verifies the identity of the data owner. If the verification succeeds, the uploaded ciphertext data is stored on a local server, and a ciphertext index, keyword ciphertext and related evidences of the data storage are uploaded to an alliance chain. The alliance chain node verifies the consistency of the uploaded transaction information, and if the verification succeeds, the transaction information is recorded.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 30, 2024
    Assignees: Zhejiang University City College, Zhejiang Gongshang University, Insititute Of Information Engineering, CAS, Zhejiang Ponshine Information Technology Co., Ltd.
    Inventors: Song Han, Siqi Ren, Haiqing Bai, Ben Niu, Xiaoli Chen
  • Patent number: 11922535
    Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Patent number: 11435400
    Abstract: A test coverage rate improvement system for pins of tested circuit board and a method thereof are disclosed. In the system, partial pins of a circuit board connector in a tested circuit board are not electrically connected to the boundary scan chip, test pins of the test pin board are pressed with the partial pins by a fixture of a boundary scan interconnect testing workstation to electrically connect the test pins to the partial pins. A test access port controller receives a detection signal for detecting the partial pins, which are not electrically connected to the boundary scan chip, of the circuit board connector through the test pin board from the test adapter card, and determines whether conduction is formed based on the detection signal, thereby achieving the technical effect of improving a test coverage rate for the pins of the tested circuit board.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 6, 2022
    Assignees: Inventec (Pudong) Technology Corporation, Inventec Corporation
    Inventors: Qiu-Yue Duan, Ben Han, Xin-Ying Xie