Patents by Inventor Ben Hertzberg
Ben Hertzberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10289469Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.Type: GrantFiled: October 28, 2016Date of Patent: May 14, 2019Assignee: Nvidia CorporationInventors: Nick Fortino, Fred Gruner, Ben Hertzberg
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Patent number: 10241810Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.Type: GrantFiled: May 18, 2012Date of Patent: March 26, 2019Assignee: Nvidia CorporationInventors: Rupert Brauch, Madhu Swarna, Ross Segelken, David Dunn, Ben Hertzberg
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Patent number: 10108424Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.Type: GrantFiled: March 14, 2013Date of Patent: October 23, 2018Assignee: Nvidia CorporationInventors: Nathan Tuck, Alexander Klaiber, Ross Segelken, David Dunn, Ben Hertzberg, Rupert Brauch, Thomas Kistler, Guillermo J. Rozas, Madhu Swarna
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Publication number: 20180121273Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventors: Nick Fortino, Fred Gruner, Ben Hertzberg
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Patent number: 9552208Abstract: A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.Type: GrantFiled: December 20, 2013Date of Patent: January 24, 2017Assignee: NVIDIA CorporationInventors: Ben Hertzberg, Guillermo Juan Rozas, Alexander Christian Klaiber, Nickolas Andrew Fortino
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Patent number: 9384001Abstract: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.Type: GrantFiled: August 15, 2012Date of Patent: July 5, 2016Assignee: NVIDIA CORPORATIONInventors: Ben Hertzberg, Nathan Tuck
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Publication number: 20150178085Abstract: A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: NVIDIA CorporationInventors: Ben Hertzberg, Guillermo Juan Rozas, Alexander Christian Klaiber, Nickolas Andrew Fortino
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Publication number: 20140281392Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: NVIDIA CORPORATIONInventors: Nathan Tuck, Alexander Klaiber, Ross Segelken, David Dunn, Ben Hertzberg, Rupert Brauch, Thomas Kistler, Guillermo J. Rozas, Madhu Swarna
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Publication number: 20140052962Abstract: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.Type: ApplicationFiled: August 15, 2012Publication date: February 20, 2014Applicant: NVIDIA CORPORATIONInventors: Ben Hertzberg, Nathan Tuck
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Publication number: 20130311752Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: NVIDIA CORPORATIONInventors: Rupert Brauch, Madhu Swarna, Ross Segelken, David Dunn, Ben Hertzberg
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Patent number: 8190845Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.Type: GrantFiled: March 14, 2011Date of Patent: May 29, 2012Assignee: Intel CorporationInventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adi-Tabatabai
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Patent number: 7908456Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.Type: GrantFiled: November 10, 2009Date of Patent: March 15, 2011Assignee: Intel CorporationInventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adi-Tabatabai
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Patent number: 7802059Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header.Type: GrantFiled: November 13, 2008Date of Patent: September 21, 2010Assignee: Intel CorporationInventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adl-Tabatabai
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Publication number: 20100122060Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.Type: ApplicationFiled: November 10, 2009Publication date: May 13, 2010Inventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adi-Tabatabai
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Patent number: 7636829Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.Type: GrantFiled: May 2, 2006Date of Patent: December 22, 2009Assignee: Intel CorporationInventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adi-Tabatabai
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Publication number: 20090077339Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header.Type: ApplicationFiled: November 13, 2008Publication date: March 19, 2009Inventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adl-Tabatabai
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Patent number: 7502897Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a block of instructions is received for execution as an object in a software transactional memory transaction. The base of the object is computed, a lock is found for the object using the base of the object.Type: GrantFiled: June 28, 2006Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adl-Tabatabai
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Publication number: 20080022054Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a block of instructions is received for execution as an object in a software transactional memory transaction. The base of the object is computed, a lock is found for the object using the base of the object.Type: ApplicationFiled: June 28, 2006Publication date: January 24, 2008Inventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adl-Tabatabai
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Publication number: 20070260608Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.Type: ApplicationFiled: May 2, 2006Publication date: November 8, 2007Inventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adi-Tabatabal