Abstract: A memory access method and an input-output memory management unit (IOMMU) are disclosed. The method includes: receiving a memory access request sent by a PCI device, which carrying a virtual address; searching for a physical address corresponding to the virtual address in its IOTLB; in a case that no corresponding physical address is found, broadcasting an address probing message carrying the virtual address to each CPU core; searching for a physical address corresponding to the virtual address in its TLB in response to the address probing message, and sending an address response message carrying the found physical address to the IOMMU after finding the physical address corresponding to the virtual address; and receiving, by the IOMMU, the address response message sent by the CPU core, storing a mapping relationship between the physical address and the virtual address in its IOTLB, and performing memory access based on the physical address.

Abstract: The present application provides a data processing method and an apparatus. In the present application, if a first estimated number of executions of a cross-cache-line operation that a VCPU allocated to a virtual machine is expected to execute on a CPU of a host machine within a first time period later is greater than a preset threshold, a function that the CPU of the host machine throws an exception due to a memory access bus of the CPU being locked is disabled first, and then a state of a detection thread is switched from a silent state to an active state, so that the detection thread polls running data of the CPU recorded in a PMU corresponding to the CPU in the host machine, and acquires an actual number of executions according to polled running data of the CPU.

Abstract: Embodiments of the present application relate to a method, device, and system for allocating resources in a server. The method includes obtaining first resource usage information associated with the first host computing system and second resource usage information associated with the second host computing system, computing a first characteristic value and a second characteristic value, wherein the first characteristic value is computed based at least in part on the first resource usage information, the second characteristic value is computed based at least in part on the second resource usage information, obtaining a first comparison result based on comparing the first characteristic value to a resource usage threshold value of the first host, and a second comparison result based on comparing the second characteristic value to a resource usage threshold value of the second host computing system, and adjusting resource allocations for the first host computing system or the second host computing system.

Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.