Abstract: Embodiments of the present application relate to a method, device, and system for allocating resources in a server. The method includes obtaining first resource usage information associated with the first host computing system and second resource usage information associated with the second host computing system, computing a first characteristic value and a second characteristic value, wherein the first characteristic value is computed based at least in part on the first resource usage information, the second characteristic value is computed based at least in part on the second resource usage information, obtaining a first comparison result based on comparing the first characteristic value to a resource usage threshold value of the first host, and a second comparison result based on comparing the second characteristic value to a resource usage threshold value of the second host computing system, and adjusting resource allocations for the first host computing system or the second host computing system.

Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.