Patents by Inventor Ben Mathew

Ben Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11449660
    Abstract: A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: September 20, 2022
    Assignee: Synopsys, Inc.
    Inventors: Jin Wu, Renu Mehra, Sabyasachi Das, Ben Mathew, Kunming Ho
  • Patent number: 7937677
    Abstract: Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: May 3, 2011
    Assignee: Synopsys, Inc.
    Inventors: Hung-Chun Chien, Ben Mathew, Padmashree Takkars, Bang Liu, Chang-Wei Tai, Xiao-Ming Xiong, Gary K. Yeap
  • Publication number: 20090288045
    Abstract: Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Applicant: Synopsys, Inc.
    Inventors: Hung-Chun Chien, Ben Mathew, Padmashree Takkars, Bang Liu, Chang-Wei Tai, Xiao-Ming Xiong, Gary K. Yeap