Patents by Inventor Ben McDavitt

Ben McDavitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12277438
    Abstract: Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: April 15, 2025
    Assignee: NETAPP, INC.
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Publication number: 20220075649
    Abstract: Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Patent number: 11182202
    Abstract: Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 23, 2021
    Assignee: NETAPP, INC.
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Publication number: 20200042347
    Abstract: Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Patent number: 10459759
    Abstract: Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 29, 2019
    Assignee: NETAPP, INC.
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Publication number: 20180165120
    Abstract: Methods, non-transitory machine-readable media, and computing devices for transitioning tasks and interrupt service routines are provided. An example method includes processing, by a plurality of processor cores of a storage controller, tasks and interrupt service routines. A performance statistic is determined corresponding to the plurality of processor cores. Based on detecting that the performance statistic passes a threshold, a number of the plurality of processor cores that are assigned to the tasks and the interrupt service routines are reduced.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 14, 2018
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Patent number: 9910700
    Abstract: A method for migration of operations between CPU cores, the method includes: processing, by a source core, one or more tasks and one or more interrupt service routines; accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines; identifying, based on the mapping, a target core that corresponds to the task and the interrupt service routine; blocking the task from being processed by the source core in response to identifying the target core; in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine; in response to identifying the target core, assigning the task and the interrupt to the target core; after assigning the interrupt to the target core, enabling the interrupt; and after assigning the task to the target core, processing the task by the target core.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 6, 2018
    Assignee: NetApp, Inc.
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Publication number: 20170090999
    Abstract: Selective multiprocessing in a non-preemptive task scheduling environment is provided. Tasks of an application are grouped based on similar functionality and/or access to common code or data structures. The grouped tasks constitute a task core group, and each task core group may be mapped to a core in a multi-core processing system. A mutual exclusion approach reduces overhead imposed on the storage controller and eliminates the risk of concurrent access. A core guard routine is used when a particular application task in a first task core group requires access to a section of code or data structure associated with a different task core group. The application task is temporarily assigned to the second task core group. The application task executes the portion of code seeking access to the section of code or data structure. Once complete, the application task is reassigned back to its original task core group.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Matthew Weber, Douglas A. Ochsner, Kam Pak, Arindam Banerjee, Ben McDavitt, Donald R. Humlicek
  • Publication number: 20170060624
    Abstract: A method for migration of operations between CPU cores, the method includes: processing, by a source core, one or more tasks and one or more interrupt service routines; accessing a mapping corresponding to a task of the one or more tasks and an interrupt service routine of the one or more interrupt service routines; identifying, based on the mapping, a target core that corresponds to the task and the interrupt service routine; blocking the task from being processed by the source core in response to identifying the target core; in response to identifying the target core, disabling an interrupt corresponding to the interrupt service routine; in response to identifying the target core, assigning the task and the interrupt to the target core; after assigning the interrupt to the target core, enabling the interrupt; and after assigning the task to the target core, processing the task by the target core.
    Type: Application
    Filed: August 26, 2015
    Publication date: March 2, 2017
    Inventors: Kent Prosch, Matthew Weber, Arindam Banerjee, Ben McDavitt
  • Patent number: 8151086
    Abstract: Disclosed is a method of detecting an access to de-allocated memory, comprising: creating a pool of fixed size memory blocks that are a non-zero integer multiple of a page size of a processor; receiving a request for an allocation of a block of memory; recording a set of allocation context information in a fixed size memory block; returning a pointer to an allocation of memory within said fixed size memory block; receiving a request to de-allocate said block of memory; recording a set of de-allocation context information in said fixed size memory block; and, setting an indicator in a page table entry associated with said fixed size memory block to a first value that indicates access to said fixed size memory block is not allowed.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: April 3, 2012
    Assignee: LSI Corporation
    Inventors: Ben McDavitt, Jeremy Zeller, Dale Harris
  • Publication number: 20100095081
    Abstract: Disclosed is a a method of detecting an access to de-allocated memory, comprising: creating a pool of fixed size memory blocks that are a non-zero integer multiple of a page size of a processor; receiving a request for an allocation of a block of memory; recording a set of allocation context information in a fixed size memory block; returning a pointer to an allocation of memory within said fixed size memory block; receiving a request to de-allocate said block of memory; recording a set of de-allocation context information in said fixed size memory block; and, setting an indicator in a page table entry associated with said fixed size memory block to a first value that indicates access to said fixed size memory block is not allowed.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 15, 2010
    Inventors: Ben McDavitt, Jeremy Zeller, Dale Harris