Abstract: Debugging systems are configured to resolve both memory aliasing conditions in which a write instruction is directed to an unknown destination address, and concurrency conditions in which control flow information is collected for multiple, concurrently executing threads. Recorded state values corresponding to an application's prior execution and control flow information are both obtained.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards a buried waveguide as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within a cladding layer. In some examples, at least one waveguide tapers along its length. In some examples, at least one waveguide includes spaced-apart segments arranged to form a subwavelength grating (SWG) configured to entrain electromagnetic radiation.

Abstract: The present disclosure provides a method of all-position plasma welding process for titanium alloy pipeline, which may be used for welding a titanium alloy pipeline made of TA2 or TC4, with a wall thickness of 3˜16 mm, and a pipe diameter of 108 mm or more. When the wall thickness is 3˜9 mm, a keyhole type technology may be used for one-time welding formation, and when the wall thickness is 9˜16 mm, grooving treatment needs to be performed for the pipeline, and the keyhole type technology is used for backing welding, and then filling welding and covering welding are performed using filler wire welding through a melt-in technology. The method includes following steps: S1: performing pre-welding treatment for the pipeline; S2: clamping the pipeline; S3: setting welding parameters; S4: starting the welding.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards a buried waveguide as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within a cladding layer. In some examples, at least one waveguide tapers along its length. In some examples, at least one waveguide includes spaced-apart segments arranged to form a subwavelength grating (SWG) configured to entrain electromagnetic radiation.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards the substrate as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within corresponding cladding layers. A first waveguide extends farther from the facet in the longitudinal direction than does a second waveguide. The second waveguide is located farther above the silicon substrate than is the first waveguide. The coupler can include a stack of waveguide assemblies. A lower waveguide assembly can include one waveguide. An intermediate or upper waveguide assembly can include multiple waveguides. In some examples, at least one waveguide tapers along its length.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards the substrate as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within corresponding cladding layers. A first waveguide extends farther from the facet in the longitudinal direction than does a second waveguide. The second waveguide is located farther above the silicon substrate than is the first waveguide. The coupler can include a stack of waveguide assemblies. A lower waveguide assembly can include one waveguide. An intermediate or upper waveguide assembly can include multiple waveguides. In some examples, at least one waveguide tapers along its length.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards a buried waveguide as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within a cladding layer. In some examples, at least one waveguide tapers along its length. In some examples, at least one waveguide includes spaced-apart segments arranged to form a subwavelength grating (SWG) configured to entrain electromagnetic radiation.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards a buried waveguide as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within a cladding layer. In some examples, at least one waveguide tapers along its length. In some examples, at least one waveguide includes spaced-apart segments arranged to form a subwavelength grating (SWG) configured to entrain electromagnetic radiation.

Abstract: A semiconductor photonic device includes a substrate, facet(s), and optical coupler(s) associated with the facet(s). Each optical coupler can couple an electromagnetic field incident on the respective facet towards the substrate as the electromagnetic field proceeds into the semiconductor photonic device. In some examples, each coupler has waveguides extending in a longitudinal direction and at least partly encapsulated within corresponding cladding layers. A first waveguide extends farther from the facet in the longitudinal direction than does a second waveguide. The second waveguide is located farther above the silicon substrate than is the first waveguide. The coupler can include a stack of waveguide assemblies. A lower waveguide assembly can include one waveguide. An intermediate or upper waveguide assembly can include multiple waveguides. In some examples, at least one waveguide tapers along its length.

Abstract: The present disclosure provides an array substrate. The array substrate includes a substrate; and at least one ultraviolet (UV) detection structure. The UV detection structure includes a photosensitive pattern on the substrate, and a first electrode pattern and a second electrode pattern for providing an operating voltage for the at least one UV detection structure.

Abstract: Subscriber Identity Module (SIM) card managing methods and electronic devices are provided. The SIM card managing method for an electronic device includes: creating a second user environment for a second user under a first user environment for a first user; and setting a predetermined SIM card for a second user via a user input. The user's privacy can thereby be well-protected.

Abstract: The present invention relates to a magnetron sputtering device, which comprises at least two targets, each of which is used for placing a target material for sputtering a film forming area of a same substrate; and magnetic field generating devices corresponding to the targets respectively and used for generating magnetic fields for controlling the directions of target sputtering particles. The magnetron sputtering device comprises at least two targets, and the target materials of the at least two targets are different from each other in composition, so that the purpose of doping different elements can be achieved by adjusting the proportion of the two target materials; by controlling the magnetic fields generated by the magnetic field generating devices, the sputtering speed and direction of the target materials can be controlled. The present invention also relates to a method for forming a film on a substrate by magnetron sputtering.

Abstract: The present disclosure provides an array substrate. The array substrate includes a substrate; and at least one ultraviolet (UV) detection structure. The UV detection structure includes a photosensitive pattern on the substrate, and a first electrode pattern and a second electrode pattern for providing an operating voltage for the at least one UV detection structure.

Abstract: The disclosed technology provides techniques for mitigating write-to-write bit error rate fluctuations that decrease accuracy of write precompensation (WPC) tuning. According to one implementation, such write-to-write bit error rate fluctuations are mitigated if a predetermined pattern is written at a particular radial offset from a target data track prior to testing a WPC register in association with the target data track. Selection of the particular radial offset can be performed according to an iterative offset track clean-up disclosed herein.

Abstract: The disclosed technology provides techniques for mitigating write-to-write bit error rate fluctuations that decrease accuracy of write precompensation (WPC) tuning According to one implementation, such write-to-write bit error rate fluctuations are mitigated if a predetermined pattern is written at a particular radial offset from a target data track prior to testing a WPC register in association with the target data track. Selection of the particular radial offset can be performed according to an iterative offset track clean-up disclosed herein.

Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.

Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.

Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.

Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.