Abstract: A field programmable device or software-defined hardware can change its functions by using software codes to alter the routing path of interconnect signal lines or the electrical properties of fundamental building elements. The field programmable device includes I/O interface blocks and signal processing blocks comprising analog signal processing units, digital signal processing units, memory units, clock units, and other supporting functional units which are electrically connected by user programmable interconnect signal lines. The analog signal processing functions can be altered by changing the electrical properties of fundamental building elements as well as the programmable signal lines after the device is manufactured.

Abstract: A field programmable device or software-defined hardware can change its functions by using software codes to alter the routing path of interconnect signal lines or the electrical properties of fundamental building elements. The field programmable device includes I/O interface blocks and signal processing blocks comprising analog signal processing units, digital signal processing units, memory units, clock units, and other supporting functional units which are electrically connected by user programmable interconnect signal lines. The analog signal processing functions can be altered by changing the electrical properties of fundamental building elements as well as the programmable signal lines after the device is manufactured.

Abstract: A nonvolatile memory device may operate with a logic transistor, which includes a transistor gate formed of a material. The memory device includes a floating gate formed of the material, a first-type fin, and a second-type fin. The first-type fin includes a first-type channel, a first-type source, and a first-type drain. The first-type channel, the first-type source, and the first-type drain have a first conductivity type. The second-type fin includes a second-type channel, a second-type source, and a second-type drain. The second-type source and the second-type drain have the first conductivity type. The second-type channel has a second conductivity type opposite to the first conductivity type. The floating gate is positioned on the first-type channel and the second-type channel.

Abstract: A nonvolatile memory device may operate with a logic transistor, which includes a transistor gate formed of a material. The memory device includes a floating gate formed of the material, a first-type fin, and a second-type fin. The first-type fin includes a first-type channel, a first-type source, and a first-type drain. The first-type channel, the first-type source, and the first-type drain have a first conductivity type. The second-type fin includes a second-type channel, a second-type source, and a second-type drain. The second-type source and the second-type drain have the first conductivity type. The second-type channel has a second conductivity type opposite to the first conductivity type. The floating gate is positioned on the first-type channel and the second-type channel.

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”).

Abstract: Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.

Abstract: The present invention relates to a method of a programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving a programming voltage and the select transistor has a select gate for receiving a select voltage. The method comprises applying the programming voltage to the control gate of the select non-volatile memory cell in a program command sequence. The magnitude of the select voltage to the select gate of the select transistor within the program command sequence is then varied. The method can be applied to non-volatile cells in a NAND or NOR architecture.

Abstract: A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines.

Abstract: The present invention relates to a method of programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving a programming voltage and the select transistor has a select gate for receiving a select voltage. The method comprises applying the programming voltage to the control gate of the select non-volatile memory cell in a program command sequence. The magnitude of the select voltage to the select gate of the select transistor within the program command sequence is then varied. The method can be applied to non-volatile cells in a NAND or NOR architecture.

Abstract: A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines.

Abstract: Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.