Patents by Inventor Ben Yau Sheen

Ben Yau Sheen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6448823
    Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of the positive charge pump is begun after the charging of the negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from a negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: September 10, 2002
    Assignee: Xilinx, Inc.
    Inventors: Farshid Shokouhi, Ben Yau Sheen, Qi Lin
  • Patent number: 6134144
    Abstract: A novel flash memory array has an array of memory cells with each memory cell being of a floating gate memory transistor with a plurality of terminals. The memory cells are arranged in a plurality of rows and a plurality of columns, with a word line connecting the memory cells in the same row. A row decoder is positioned adjacent one side of the memory array and is connected to the plurality of word lines for receiving an address signal and for supplying a low voltage signal. A plurality of programming lines are connected to the plurality of rows of memory cells of the array with a programming line connected to the memory cells in the same row. The plurality of programming lines are collinear with but spaced apart from the plurality of word lines and extending only to the row decoder.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: October 17, 2000
    Assignee: Integrated Memory Technologies, Inc.
    Inventors: Tien L. Lin, Ben Yau Sheen