Abstract: A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency.

Abstract: A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency.

Abstract: A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) having a first clock input, a second clock input, and a TDC output. The DPLL includes a digital loop filter (DLF). The DLF output controls a numerically-controlled bulk acoustic wave oscillator (NCBO). The NCBO output is divided down a fractional-N divider and is fed back to the TDC. The NCBO includes a reference oscillator, a phase and/or frequency detector, a charge pump, a loop filter, a voltage-controlled bulk acoustic wave oscillator (VCBO) and a feedback fractional-N divider that has a numerical control input, which is controlled by DLF output of DPLL. The NCBO forms a stable feedback loop and have a loop bandwidth much wider than DPLL loop bandwidth. In steady state, the NCBO output frequency can be linearly numerically adjusted. An auxiliary PLL or a fractional output divider can be used to generate additional needed frequencies.

Abstract: A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency.

Abstract: A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency.

Abstract: A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.

Abstract: An apparatus for acquiring analytes from a dried biological fluid sample includes a tube, a substrate in a proximal section of the tube, and a sorbent bed in a distal section of the tube. A biological fluid sample is dispensed on the substrate and is dried to form a dried sample. A conditioning solvent is flowed into the distal section to condition the sorbent bed. A first elution solvent is flowed through the substrate and the sorbent bed. Analytes are eluted from the dried sample and retained on the sorbent bed. A second elution solvent is flowed through the substrate and the sorbent bed. The analytes are eluted from the sorbent bed, pass through an opening, and are collected. Alternatively, an elution solvent is flowed through the substrate and the sorbent bed such that analytes eluted from the dried sample pass through the sorbent bed and the opening for collection, while non-analytes are retained on the sorbent bed.

Abstract: A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.