Abstract: A Language Controlled Design Flow for the development of integrated circuits (IC) that allows users to Characterize, Synthesize, Simulate, and Analyze IC designs. The Language Controlled Design Flow provides specialized features that enable rapid design development and Intellectual Property (IP) reuse. The language provides the ability to capture a designer's knowledge about the Design Components and Design Processes unique to those components during characterization, synthesis, simulation, and analysis. A feature of this invention is the ability to separate design or design component specific knowledge from the tools used for analysis. This leads to benefits in extensibility, simplicity, accuracy, and performance of the overall tool set. Also provided is a mechanism in which the design process can be fully automated with a Language Controlled Design Flow that can take advantage of the information available in the design, in the design components, and in the design process flow.

Abstract: The described invention relates to a phase-locked loop circuit arrangement for synchronizing an oscillator to a Non-Return-To-Zero data signal in which a transition from one potential level to another represents a data transition from one binary value to another.A local clock signal is provided by means of a controllable oscillator and a phase comparator compares the phases of the data and clock singals with one another. The frequency of the oscillator is adjusted by means of a control signal in dependence upon an amount by which the phase of the data leads that of the clock signal and vice versa. In any cycle of the clock signal in which the phase of the clock signal leads that of the data and in which no data transition occurs the application of a control signal to the oscillator is inhibited.The invention is particularly applicable to teletext receivers.