Abstract: Systems, apparatuses, and methods for low wander timing generation and/or recovery are disclosed here. In one aspect, embodiments of the present disclosure include a communication system for high speed communications between a first location and a second location. The communication system, may include a transmitter module at the first location associated a first clock and/or a receiver module at the second location associated with the second clock.

Abstract: A system for providing subscriber line power to an auxiliary device may include a primary communications device, a secondary communications device, and an auxiliary device. The primary communications device and the secondary communications device may be connected to opposite ends of at least one subscriber line. The auxiliary device may be connected to the secondary communications device. The auxiliary device may be powered by the primary communications device via the subscriber line and the secondary communications device. A power capacity metric of the at least one subscriber line may be determined. An operating power metric of the secondary communications device may be determined. A power budget may be calculated from the power capacity metric and the operating power metric. The power budget may be enforced. For example, the secondary communications device may limit power to the auxiliary device to enforce the power budget.

Abstract: The present invention teaches a variety of timing generation and recovery schemes for providing high precision clock synchronization in cascaded communications systems where each point of communication has a unique clock. To accomplish the high precision, one embodiment of the present invention teaches quantizing information related to phase relation between a master clock at the transmitter and a network link clock. This quantized phase information can be transmitted with very little bandwidth, recovered and the receiver and used to recover the timing information with high precision.

Abstract: Systems, apparatuses, and methods for low wander timing generation and/or recovery are disclosed here. In one aspect, embodiments of the present disclosure include a communication system for high speed communications between a first location and a second location. The communication system, may include a transmitter module at the first location associated a first clock. The transmitter module may further include a phase detector module that is operable to generate a one or more data bits to indicate phase offset between the first clock and a second clock, the first clock can be associated with a transmission rate and the second clock can be associated with a network link rate and/or a receiver module at the second location associated with the second clock. The receiver module may be coupled to the transmitter module via a network.

Abstract: A noise cancellation system configured to isolate and process a common mode noise signal to generate a cancellation signal. The cancellation signal is combined with a differential signal to cancel unwanted differential mode noise that coupled onto the differential signal. In one embodiment a multi-channel communication system utilizes two or more channels that are in close proximity to other alien channels. A common mode signal isolation unit is configured to isolate common mode noise. The common mode noise signal is processed with a filter or other means to generate a cancellation signal. The cancellation signal is combined with the differential signal to thereby cancel noise that coupled onto the differential signal. The processed common mode noise signal may be made to approximate the differential mode noise signal. The common mode signal may be obtained from a center tap of a transformer, or a sensing winding of a three winding transformer.

Abstract: A line powering system for a multi-channel communication system is disclosed having a central office or primary communication terminal configured to communicate with one or more remote locations via two or more communication lines. Line powering, from the primary location to the remote location, is provided by a power supply, which is selectively connected to one or more of the lines via a switching module. Line monitoring and switch control may occur automatically or by a controller. A ground fault detector is provided to monitor for excessive ground fault current and selectively disconnect the faulted line. A rapid line voltage discharge module is provided to discharge line voltage to meet specification.

Abstract: An analog front end system comprising a digital-to-analog converter, a line driver, a multiple-input device, and an analog-to-digital converter is presented. Furthermore, a method for DSL line testing comprising the steps of providing test stimuli to and receiving responses from a DSL line using an analog front end is presented. The presented system and method provides for the testing of a DSL line in an xDSL communications system deployment.

Abstract: The present invention teaches a variety of timing generation and recovery schemes for providing high precision clock synchronization in cascaded communications systems where each point of communication has a unique clock. To accomplish the high precision, one embodiment of the present invention teaches quantizing information related to phase relation between a master clock at the transmitter and a network link clock. This quantized phase information can be transmitted with very little bandwidth, recovered and the receiver and used to recover the timing information with high precision.

Abstract: A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

Abstract: A noise cancellation system configured to isolate and process a common mode noise signal to generate a cancellation signal. The cancellation signal is combined with a differential signal to cancel unwanted differential mode noise that coupled onto the differential signal. In one embodiment a multi-channel communication system utilizes two or more channels that are in close proximity to other alien channels. A common mode signal isolation unit is configured to isolate common mode noise. The common mode noise signal is processed with a filter or other means to generate a cancellation signal. The cancellation signal is combined with the differential signal to thereby cancel noise that coupled onto the differential signal. The processed common mode noise signal may be made to approximate the differential mode noise signal. The common mode signal may be obtained from a center tap of a transformer, or a sensing winding of a three winding transformer.

Abstract: A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

Abstract: A coordinated timing technique is disclosed which allows a single analog-to-digital converter (ADC) to be timeshared by multiple digital transceivers operating on independent subscriber loops with independent sampling phase requirements. The multiple transceivers must all operate from a single master reference clock. However, any arbitrary timing phase relationship between the transceivers can be accommodated.

Abstract: A frequency synthesizer for producing an output whose phase and/or frequency can be finely adjusted under digital control. The synthesizer utilizes a phase lock loop including a phase detector responsive to a prescale divide-by-N frequency divider and a feedback divide-by-M frequency divider to product an output signal F.sub.OUT. The phase of F.sub.OUT can be shifted by a small increment by slightly adjusting the values of the divisors M and N.

Abstract: A phase-locked loop frequency synthesizer apparatus for providing an output signal whose frequency jumps from one value to another, at regular intervals of time. Coarse tuning circuitry couples a prescribed signal to the apparatus' voltage-controlled oscillator (VCO), to drive the VCO immediately to the correct frequency each time a new frequency is selected, thereby substantially reducing the apparatus' settling time. In addition, adaptive coarse tuning circuitry continuously updates the values of stored coarse tuning information for each possible frequency, to correct for any drifts in the VCO's voltage/frequency characteristic. A VCO gain normalizer circuit amplifies the error signal coupled to the VCO by an amount that varies with the selected frequency, so as to correct for any non-uniformities in the apparatus' various elements, particularly the VCO, and to thereby provide a uniform loop gain.