Abstract: A circuit for converting high voltage AC to low voltage DC has an input capacitor coupled an input AC source. A rectifier is coupled to the input capacitor. A switch is coupled to the rectifier. A voltage regulator is coupled to the switch. The voltage regulator regulates an output of the circuit by closing the switch when a rising edge of a rectified AC voltage is below an output voltage and opens the switch when the output voltage reaches a regulation voltage. A storage capacitor is coupled to the switch.

Abstract: A complementary high voltage switched current source circuit has a complementary current source pair, wherein a first of the current source pair is coupled to a positive voltage rail and a second of the current source pair is coupled to a negative voltage rail. A digital logic-level control interface circuit is coupled to the complementary current source pair and to the positive voltage rail and the negative voltage rail. A pair of high voltage switches is coupled to the complementary current source pair and the digital logic-level control interface circuit and controlled by the digital control interface circuit.

Abstract: A ultrasound transmit pulse waveform generator for driving a piezoelectric transducer in medical ultrasound imaging, nondestructive testing (NDT) ultrasound imaging applications, includes a capacitor, switching programmable current sources, and a power amplifier.

Abstract: The present invention relates to a high voltage output circuit for driving a gray scale flat panel display. The high voltage output circuit eliminates the inaccuracies of prior art output circuits by using a plurality of transistors to eliminate a dead band level within the output circuit. The output circuit is also less expensive than prior art output circuits since a level translator is not required.

Abstract: Method and structure is disclosed for a high-density DMOS transistor with an improved body contact. The improvement comprises a self-aligned structure in combination with a body contact region which overdopes the source region in order to minimize the number of critical photoresist steps. The use of two dielectric spacers obviates the need for a separate contact mask.

Abstract: A high-voltage level translator circuit is disclosed that is suitable for monolithic integration. The level translator circuit comprises serially-connected current sources suitably ratioed so that the gating on of one current source causes a limited voltage rise across the other current source, which is ungated. The circuit is suitable for integration in a junction-isolated monolithic pseudo-complementary CMOS format.

Abstract: This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device.

Abstract: This disclosure relates to an improved DMOS semiconductor type device which can function both as a DMOS (unipolar) type device and as a bipolar transistor device. The DMOS device has two separated source regions of, for example, N+ conductivity and each of these source regions is surrounded by a P- type region, thus providing a pair of channels between each N+ source region and a common N type drain region located between the P- regions. A gate electrode is disposed over both of the channels and functions to permit electrons from the N+ source regions to flow across the P- channels into the common N type drain region when a proper bias is applied to the gate region. Each of the source regions has its own electrode and a separate electrode is provided to each of the P- regions that surround each of the respective N+ source regions.

Abstract: This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V grooves.