Patents by Inventor Benedict C. Lau

Benedict C. Lau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory controller with staggered request signal output
    Patent number: 11830573
    Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: November 28, 2023
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20220343956
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 27, 2022
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory device with circuitry to transmit feedback indicative of a phase relationship
    Patent number: 11302368
    Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 12, 2022
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20210193197
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: November 19, 2020
    Publication date: June 24, 2021
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 10902891
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: January 26, 2021
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20200294559
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 17, 2020
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 10593379
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20190088295
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: August 22, 2018
    Publication date: March 21, 2019
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 10062421
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: August 28, 2018
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20170352390
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: June 17, 2017
    Publication date: December 7, 2017
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 9691447
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: June 27, 2017
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20160012869
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: September 23, 2015
    Publication date: January 14, 2016
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 9165617
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 20, 2015
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20140173240
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: January 13, 2014
    Publication date: June 19, 2014
    Applicant: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 8638637
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 28, 2014
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Integrated circuit with staggered signal output
    Patent number: 8339878
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 25, 2012
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT
    Publication number: 20120188835
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: December 23, 2011
    Publication date: July 26, 2012
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Memory controller with staggered request signal output
    Patent number: 8089824
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: January 3, 2012
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Phase synchronization for wide area integrated circuits
    Patent number: 7932755
    Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: April 26, 2011
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Benedict C. Lau, Leung Yu, Jade M. Kizer
  • MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    Publication number: 20090238025
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Application
    Filed: June 3, 2009
    Publication date: September 24, 2009
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau