Abstract: Methods and systems are provided for inferring types in a computer program. In one example, a method comprises: identifying a type of at least one expression of the computer program; and annotating the at least one expression in the computer program when the type of the at least one expression is at least one of a varying type and a uniform type.

Abstract: A method, computer program product, and system is described that determines the correctness of using memory operations in a computing device with heterogeneous computer components. Embodiments include an optimizer based on the characteristics of a Sequential Consistency for Heterogeneous-Race-Free (SC for HRF) model that analyzes a program and determines the correctness of the ordering of events in the program. HRF models include combinations of the properties: scope order, scope inclusion, and scope transitivity. The optimizer can determine when a program is heterogeneous-race-free in accordance with an SC for HRF memory consistency model . For example, the optimizer can analyze a portion of program code, respect the properties of the SC for HRF model, and determine whether a value produced by a store memory event will be a candidate for a value observed by a load memory event. In addition, the optimizer can determine whether reordering of events is possible.

Abstract: A device receives input that includes definitions of components of a computational pipeline, where the components include one or more buffers, one or more kernels, and one or more stages within a control graph. The device generates, based on the input, kernel signatures for a graphics processor, where the kernel signatures compile into an executable streaming program for the computational pipeline. The device also generates, based on the input, host-side runtime code to execute the streaming program.

Abstract: Methods, systems, and computer readable storage media embodiments allow for low overhead context switching of threads. In embodiments, applications, such as, but not limited to, iterative data-parallel applications, substantially reduce the overhead of context switching by adding a user or higher-level program configurability of a state to be saved upon preempting of a executing thread. These methods, systems, and computer readable storage media include aspects of running a group of threads on a processor, saving state information by respective threads in the group in response to a signal from a scheduler, and pre-empting running of the group after the saving of the state information.

Abstract: Some embodiments include a processing subsystem that compiles program code to generate compiled program code. In these embodiments, while compiling the program code, the processing subsystem first identifies a pointer in the program code that points to an unspecified address space. The processing subsystem then analyzes at least a portion of the program code to determine one or more address spaces to which the pointer may point. Next, the processor updates metadata for the pointer to indicate the one or more address spaces to which the pointer may point, the metadata enabling a determination of an address space to which the pointer points during subsequent execution of the compiled program code.

Abstract: With the success of programming models such as OpenCL and CUDA, heterogeneous computing platforms are becoming mainstream. However, these heterogeneous systems are low-level, not composable, and their behavior is often implementation defined even for standardized programming models. In contrast, the method and system embodiments for the heterogeneous parallel primitives (HPP) programming model disclosed herein provide a flexible and composable programming platform that guarantees behavior even in the case of developing high-performance code.

Abstract: Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.

Abstract: Disclosed methods, systems, and computer program products embodiments include synchronizing a group of workitems on a processor by storing a respective program counter associated with each of the workitems, selecting at least one first workitem from the group for execution, and executing the selected at least one first workitem on the processor. The selecting is based upon the respective stored program counter associated with the at least one first workitem.

Abstract: In a computing system, memory may be managed by using a distributed array, which is a global set of local memory regions. A segment in the distributed array is allocated and is bound to a physical memory region. The segment is used by a workgroup in a dispatched data parallel kernel, wherein a workgroup includes one or more work items. When the distributed array is declared, parameters of the distributed array may be defined. The parameters may include an indication whether the distributed array is persistent (data written to the distributed array during one parallel dispatch is accessible by work items in a subsequent dispatch) or an indication whether the distributed array is shared (nested kernels may access the distributed array). The segment may be deallocated after it has been used.

Abstract: A system, method, and computer program product are provided for improving resource utilization of multithreaded applications. Rather than requiring threads to block while waiting for data from a channel or requiring context switching to minimize blocking, the techniques disclosed herein provide an event-driven approach to launch kernels only when needed to perform operations on channel data, and then terminate in order to free resources. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.

Abstract: A computer system is provided for compiling program code and a method for compiling program code by a processor. The method, for example, includes, but is not limited to, receiving, by the processor, the program code and compiling, by the processor, the program code, wherein the processor, when compiling the program code, parses the program code and assigns a default address space qualifier to each member functions without a defined address space qualifier and, when the member function is used, infers an address space for each default address qualifier based upon how the respective member function is being used.

Abstract: Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.

Abstract: A medium and method is disclosed for compiling vector programs. A compiler receives program code that includes a function invocation. The compiler determines the vector width of a target computer system and creates a width-specific executable version of the program code by mapping the function invocation to a width-specific implementation of the function. The width-specific implementation corresponds to the vector width of the target computer system.

Abstract: A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent invocation of a function. The compiler creates a width-specific executable version of the program code by determining a vector width of a target computer system and omitting the function from the width-specific executable if the vector width meets one or more criteria. For example, the compiler may omit the function call if the vector width is greater than a minimum size.

Abstract: A device receives input that includes definitions of components of a computational pipeline, where the components include one or more buffers, one or more kernels, and one or more stages within a control graph. The device generates, based on the input, kernel signatures for a graphics processor, where the kernel signatures compile into an executable streaming program for the computational pipeline. The device also generates, based on the input, host-side runtime code to execute the streaming program.