Abstract: In a shift register latch scan string such as that employed in level sensitive scan design (LSSD) methodologies, primary input and/or primary output signal line connections are distributed in a substantially uniform fashion along the length of the shift register scan string configuration so as to provide a mechanism for testing for fault conditions existing along the scan string.

Abstract: Logic fencing circuit and method are provided for increasing system protection at a multiprocessor system interface so that spurious noise (e.g., attributable to an electrostatic discharge through a signal cable) is more reliably isolated from an active portion of the processing system. The noise fencing circuit, which is responsive to a fence control signal, includes logic circuitry for attenuating a received noise signal by constraining the noise signal to a magnitude less than or equal to the voltage level of a system power supply. The attenuating circuitry outputs an attenuated noise signal to a signal fence circuit which, when enabled by the fence control signal, outputs a substantially constant isolation signal in response to a received, attenuated noise signal. A logically staged fencing method is also set forth.

Abstract: A static dissipative electrical cable which eliminates the build-up of triboelectric charging by having a carbon loaded outer jacket which is a semiconductor for draining off triboelectric charges. In one embodiment, the jacket material is a 1 megohm/ft semiconductive extrudable Teflon polyfluorinated alkoxy (PFA) resin static-dissipative polymer of low carbon-black loading (3-4% by weight) having very stable electrical/mechanical properties against temperature excursions, thermal/environmental shock and aging. The cable is designed with a double-clad aluminum/mylar foil shield that allows electrical commoning between inner and outer clads of the foil and control of the interface between semi-conductive static-dissipative jacket and the foil shield to yield a jacket-to-ground wire resistance value between 100 kilo-ohms and 50 megohms.

Abstract: A fast path (comprising control and data busses) directly connects between a storage element in a storage hierarchy and a requestor. The fast path (FP) is in parallel with the bus path normally provided through the storage hierarchy between the requestor and the storage element controller. The fast path may bypass intermediate levels in the storage hierarchy. The fast path is used at least for fetch requests from the requestor, since fetch requests have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path in a system to decrease the peak loads on the normal path. A requestor using the fast path makes each fetch request simultaneously to the fast path and to the normal path in a system controller element (SCE). The request through the fast path gets to the storage element before the same request through the SCE, but may be ignored by the storage element if it is busy.

Abstract: A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.

Abstract: The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP. The data transfers can occur in parallel among plural CPU caches, channel processors and main storage (MS) sections using crosspoint switches in a manner which utilizes the high circuit count of LSI modules without substantially utilizing the module I/O pin count to enable MP structures to contain more CPUs than could be contained with conventional bussing.

Abstract: Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS).Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage.In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands.

Abstract: A fast synonym detection and handling mechanism is disclosed for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into 2.sup.N groups of classes, in which N is the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the 2.sup.N groups. The selected class entries are simultaneously compared with one or more dynamic lookaside address translator (DLAT) translated absolute addresses. Compare signals, one for each class entry per DLAT absolute address, are routed to a synonym detection circuit. The detection circuit simultaneously interprets all directory compare signals and determines if a principle hit, synonym hit or a miss occurred in the cache for each request.

Abstract: A cache organization that enables many cache functions to overlap without extending line fetch or line castout time and without requiring a cache technology faster than the processor technology. Main storage has a data bus-out and a data bus-in, each transferring a double word (DW) in one cycle. Both busses may transfer respective DWs in opposite directions in the same cycle. The cache has a quadword (QW) write register and a QW read register, a QW being two DWs on a QW address boundary. During a line fetch (LF) of 16DWs, either the first pair of DWs, or the first DW of the LF is loaded into the QW write register, depending on whether the first DW is on a QW address boundary or not, i.e., whether the fetch request address bit 28 is even or odd, respectively. Thereafter during the LF, the even and odd DWs are formed into QWs as received from the bus-out, and the QWs are written into the cache on alternate cycles, wherein no QW cache access occurs on the other alternate cycles for the LF.

Abstract: Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 valid binary bit combinations that reflect the sequence of use of the four units. The provision of 6 binary bits in the LRU code are capable of assuming 64 different permutations, therefore 40 combinations of binary bits are considered invalid when utilizing the LRU code.

Abstract: This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.