Patents by Inventor Benedikt Geukes
Benedikt Geukes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Automating addition of power supply rails, fences, and level translators to a modular circuit design
Patent number: 11907634Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.Type: GrantFiled: September 1, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Gavin B. Meil, Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine -
Patent number: 11663381Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.Type: GrantFiled: September 7, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Stephen Gerard Shuma, Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Benedikt Geukes, Klaus-Dieter Schubert, Birgit Schubert, Stephen John Barnfield, Derek E. Williams
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AUTOMATING ADDITION OF POWER SUPPLY RAILS, FENCES, AND LEVEL TRANSLATORS TO A MODULAR CIRCUIT DESIGN
Publication number: 20230072459Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.Type: ApplicationFiled: September 1, 2021Publication date: March 9, 2023Inventors: Gavin B. Meil, Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine -
Publication number: 20230074528Abstract: A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Stephen Gerard Shuma, Stephen John Barnfield, Maya Safieddine, Benedikt Geukes, Klaus-Dieter Schubert, Gabor Drasny
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Publication number: 20230075770Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Stephen Gerard Shuma, Ali S. El-Zein, Wolfgang Roesner, Viresh Paruthi, Benedikt Geukes, Klaus-Dieter Schubert, Birgit Schubert, Stephen John Barnfield, Derek E. Williams
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Publication number: 20230070516Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Viresh Paruthi, Alvan Wing Ng, Benedikt Geukes, Klaus-Dieter Schubert, Robert Alan Cargnoni, Michael Hemsley Wood, Stephen Gerard Shuma, Wolfgang Roesner, Chung-Lung K. Shum, Edward Armayor McQuade, Derek E. Williams
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Patent number: 10838449Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.Type: GrantFiled: July 5, 2018Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Matteo Michel, Manfred Walz
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Patent number: 10658062Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: GrantFiled: September 11, 2019Date of Patent: May 19, 2020Assignee: International Business Machines CorporationInventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Patent number: 10586606Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: GrantFiled: January 2, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Publication number: 20200012312Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Inventors: BENEDIKT GEUKES, MATTEO MICHEL, MANFRED WALZ
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Publication number: 20200005883Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: ApplicationFiled: September 11, 2019Publication date: January 2, 2020Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Publication number: 20190156907Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: ApplicationFiled: January 2, 2019Publication date: May 23, 2019Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Patent number: 10199121Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: GrantFiled: May 8, 2018Date of Patent: February 5, 2019Assignee: International Business Machines CorporationInventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Patent number: 10156610Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: GrantFiled: May 3, 2017Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180321314Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Inventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180321315Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.Type: ApplicationFiled: December 7, 2017Publication date: November 8, 2018Inventors: Benedikt Geukes, Manfred Walz, Matteo Michel
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Publication number: 20180294042Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: ApplicationFiled: May 8, 2018Publication date: October 11, 2018Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Publication number: 20180294041Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: ApplicationFiled: December 27, 2017Publication date: October 11, 2018Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Patent number: 10096377Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: GrantFiled: December 27, 2017Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
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Patent number: 10026498Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.Type: GrantFiled: April 10, 2017Date of Patent: July 17, 2018Assignee: International Business Machines CorporationInventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal