Patents by Inventor Benfu Lin
Benfu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10693054Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.Type: GrantFiled: July 26, 2018Date of Patent: June 23, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
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Publication number: 20200035906Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Danny Pak-Chum SHUM, Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Juan Boon TAN, Benfu LIN
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Patent number: 10342854Abstract: A leptin active peptide having CD-loop and helix E region mutations, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having CD-loop and helix E region mutations is shown in SEQ ID NO.1.Type: GrantFiled: November 6, 2017Date of Patent: July 9, 2019Assignee: SHANGHAI YUANXIN BIOCHEMICAL SCIENCE AND TECHNOLOGY CO. LTD.Inventors: Lihong Yuan, Jiahai Lu, Benfu Lin
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Patent number: 10342853Abstract: A leptin active peptide having helix D region mutation, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having helix D region mutation is shown in SEQ ID NO.1.Type: GrantFiled: November 6, 2017Date of Patent: July 9, 2019Assignee: SHANGHAI YUANXIN BIOCHEMICAL SCIENCE AND TECHNOLOGY CO. LTD.Inventors: Lihong Yuan, Jiahai Lu, Benfu Lin
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Publication number: 20180233661Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and forming a dielectric layer over the substrate. An alignment mark opening which extends through the dielectric layer is formed. A conductive layer is deposited over the dielectric layer. A planarization process is performed to remove excess conductive material on the dielectric layer and recess a top surface of the conductive material in the alignment mark opening with respect to the dielectric layer, forming an alignment mark of the device. A first electrode layer may be formed over the dielectric layer, wherein a topography of the dielectric layer and the alignment mark in the dielectric layer is transferred to the first electrode layer.Type: ApplicationFiled: February 15, 2017Publication date: August 16, 2018Inventors: Benfu LIN, Kah Wee GAN, Chim Seng SEET
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Patent number: 9997562Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.Type: GrantFiled: March 14, 2017Date of Patent: June 12, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lei Wang, Benfu Lin, Chim Seng Seet, Kai Hung Alex See
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Publication number: 20180050093Abstract: A leptin active peptide having helix D region mutation, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having helix D region mutation is shown in SEQ ID NO. 1.Type: ApplicationFiled: November 6, 2017Publication date: February 22, 2018Inventors: LIHONG YUAN, JIAHAI LU, BENFU LIN
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Publication number: 20180050094Abstract: A leptin active peptide having CD-loop and helix E region mutations, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having CD-loop and helix E region mutations is shown in SEQ ID NO.1.Type: ApplicationFiled: November 6, 2017Publication date: February 22, 2018Inventors: LIHONG YUAN, JIAHAI LU, BENFU LIN
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Patent number: 9711662Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming an upper interlayer dielectric overlying an optical modulator and a photodetector, where the photodetector has a shoulder and a plug. An etch stop is formed overlying the upper interlayer dielectric. The etch stop is a first, second, and third distance from an uppermost surface of the optical modulator, the shoulder, and the plug, respectively, where the first, second, and third distances are all different from each other. A first, second, and third contact are formed through the upper interlayer dielectric, where the first, second and third contacts are in electrical communication with the optical modulator, the shoulder, and the plug, respectively.Type: GrantFiled: April 21, 2016Date of Patent: July 18, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Benfu Lin, Juan Boon Tan, Ramakanth Alapati
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Patent number: 9520371Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.Type: GrantFiled: October 27, 2014Date of Patent: December 13, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Benfu Lin, Wanbing Yi, Wei Lu, Alex See, Juan Boon Tan
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Patent number: 9511474Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.Type: GrantFiled: January 25, 2016Date of Patent: December 6, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Benfu Lin, Wei Lu, Alex See
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Patent number: 9511470Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.Type: GrantFiled: January 25, 2016Date of Patent: December 6, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
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Patent number: 9437547Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.Type: GrantFiled: March 8, 2016Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
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Publication number: 20160190066Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Inventors: Benfu LIN, Hong YU, Lup San LEONG, Alex SEE, Wei LU
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Publication number: 20160136774Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Benfu LIN, Lei WANG, Xuesong RAO, Wei LU, Alex SEE
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Publication number: 20160136781Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Benfu Lin, Wei Lu, Alex See
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Publication number: 20160118355Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.Type: ApplicationFiled: October 27, 2014Publication date: April 28, 2016Inventors: Benfu LIN, Wanbing YI, Wei LU, Alex SEE, Juan Boon TAN
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Patent number: 9287197Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.Type: GrantFiled: March 15, 2013Date of Patent: March 15, 2016Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
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Patent number: 9242338Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.Type: GrantFiled: October 22, 2013Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
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Patent number: 9242341Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.Type: GrantFiled: October 22, 2013Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Benfu Lin, Wei Lu, Alex See