Patents by Inventor Benfu Lin

Benfu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10693054
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
  • Publication number: 20200035906
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventors: Danny Pak-Chum SHUM, Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Juan Boon TAN, Benfu LIN
  • Patent number: 10342854
    Abstract: A leptin active peptide having CD-loop and helix E region mutations, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having CD-loop and helix E region mutations is shown in SEQ ID NO.1.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 9, 2019
    Assignee: SHANGHAI YUANXIN BIOCHEMICAL SCIENCE AND TECHNOLOGY CO. LTD.
    Inventors: Lihong Yuan, Jiahai Lu, Benfu Lin
  • Patent number: 10342853
    Abstract: A leptin active peptide having helix D region mutation, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having helix D region mutation is shown in SEQ ID NO.1.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 9, 2019
    Assignee: SHANGHAI YUANXIN BIOCHEMICAL SCIENCE AND TECHNOLOGY CO. LTD.
    Inventors: Lihong Yuan, Jiahai Lu, Benfu Lin
  • Publication number: 20180233661
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and forming a dielectric layer over the substrate. An alignment mark opening which extends through the dielectric layer is formed. A conductive layer is deposited over the dielectric layer. A planarization process is performed to remove excess conductive material on the dielectric layer and recess a top surface of the conductive material in the alignment mark opening with respect to the dielectric layer, forming an alignment mark of the device. A first electrode layer may be formed over the dielectric layer, wherein a topography of the dielectric layer and the alignment mark in the dielectric layer is transferred to the first electrode layer.
    Type: Application
    Filed: February 15, 2017
    Publication date: August 16, 2018
    Inventors: Benfu LIN, Kah Wee GAN, Chim Seng SEET
  • Patent number: 9997562
    Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: June 12, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lei Wang, Benfu Lin, Chim Seng Seet, Kai Hung Alex See
  • Publication number: 20180050093
    Abstract: A leptin active peptide having helix D region mutation, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having helix D region mutation is shown in SEQ ID NO. 1.
    Type: Application
    Filed: November 6, 2017
    Publication date: February 22, 2018
    Inventors: LIHONG YUAN, JIAHAI LU, BENFU LIN
  • Publication number: 20180050094
    Abstract: A leptin active peptide having CD-loop and helix E region mutations, a coding gene thereof, and an application thereof are provided in the present invention. An amino acid sequence of the leptin active peptide having CD-loop and helix E region mutations is shown in SEQ ID NO.1.
    Type: Application
    Filed: November 6, 2017
    Publication date: February 22, 2018
    Inventors: LIHONG YUAN, JIAHAI LU, BENFU LIN
  • Patent number: 9711662
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming an upper interlayer dielectric overlying an optical modulator and a photodetector, where the photodetector has a shoulder and a plug. An etch stop is formed overlying the upper interlayer dielectric. The etch stop is a first, second, and third distance from an uppermost surface of the optical modulator, the shoulder, and the plug, respectively, where the first, second, and third distances are all different from each other. A first, second, and third contact are formed through the upper interlayer dielectric, where the first, second and third contacts are in electrical communication with the optical modulator, the shoulder, and the plug, respectively.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Benfu Lin, Juan Boon Tan, Ramakanth Alapati
  • Patent number: 9520371
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 13, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Wanbing Yi, Wei Lu, Alex See, Juan Boon Tan
  • Patent number: 9511474
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Wei Lu, Alex See
  • Patent number: 9511470
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
  • Patent number: 9437547
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
  • Publication number: 20160190066
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: Benfu LIN, Hong YU, Lup San LEONG, Alex SEE, Wei LU
  • Publication number: 20160136774
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Application
    Filed: January 25, 2016
    Publication date: May 19, 2016
    Inventors: Benfu LIN, Lei WANG, Xuesong RAO, Wei LU, Alex SEE
  • Publication number: 20160136781
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Application
    Filed: January 25, 2016
    Publication date: May 19, 2016
    Inventors: Benfu Lin, Wei Lu, Alex See
  • Publication number: 20160118355
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Benfu LIN, Wanbing YI, Wei LU, Alex SEE, Juan Boon TAN
  • Patent number: 9287197
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
  • Patent number: 9242338
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
  • Patent number: 9242341
    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Benfu Lin, Wei Lu, Alex See