Abstract: The present invention provides an integrated circuit for communication, e.g., for mobile radio-frequency (RF) telecommunication, including a resonator, a main amplifier, a matching circuit, a blocker detector, a mixer circuit, and a translation filter. The resonator provides conversion from single-end to differential, and filtering function for rejecting blockers at harmonics of local oscillation signal. The blocker detector detects occurrence of blocker; according to whether blocker exists, the main amplifier amplifies differential signal of the resonator by different gains, and the mixer circuit mixes amplified signal with different numbers of mixers. The translation filter contributes to rejection of blockers closed to in-band by providing a first pass band which is translated to a second pass band by the mixer circuit. The matching circuit provides impedance match.

Abstract: The present invention provides an integrated circuit for communication, e.g., for mobile radio-frequency (RF) telecommunication, including a resonator, a main amplifier, a matching circuit, a blocker detector, a mixer circuit, and a translation filter. The resonator provides conversion from single-end to differential, and filtering function for rejecting blockers at harmonics of local oscillation signal. The blocker detector detects occurrence of blocker; according to whether blocker exists, the main amplifier amplifies differential signal of the resonator by different gains, and the mixer circuit mixes amplified signal with different numbers of mixers. The translation filter contributes to rejection of blockers closed to in-band by providing a first pass band which is translated to a second pass band by the mixer circuit. The matching circuit provides impedance match.

Abstract: An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

Abstract: A receiver includes a mixer, a poly phase filter, a channel select filter, an analog-to-digital converter and a HI/LO side reject selection unit. The mixer downconverts a signal to generate an in-phase signal and a quadrature signal. The poly phase filter for generates differential IF signals based on the in-phase signal and the quadrature signal. The channel select filter filters out unwanted channel signals from the differential IF signals. The analog-to-digital converter converts the filtered signal into a digital output signal. The HI/LO side reject selection unit is coupled between the mixer and the poly phase filter and capable of rejecting image signals while the mixer is at a high side frequency or at a low side frequency.

Abstract: A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

Abstract: A system capable of limiting a current through a load and a method thereof. The system comprises a current sensor, a determination circuit, and a current mirror circuit. The current sensor, coupled to the load, produces a current indication indicating the current. The determination circuit, coupled to the current sensor, generates a short-circuit signal when the current exceeds a predetermined threshold. The current mirror circuit, coupled to a voltage source, the current sensor and the determination circuit, comprises a current mirror and a bypass path, delivers a mirrored current from the current mirror to the load upon receiving the short-circuit signal, and passes the current from the voltage source through the bypass path to the load in the absence of the short-circuit signal.

Abstract: An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

Abstract: A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

Abstract: A system capable of limiting a current through a load and a method thereof. The system comprises a current sensor, a determination circuit, and a current mirror circuit. The current sensor, coupled to the load, produces a current indication indicating the current. The determination circuit, coupled to the current sensor, generates a short-circuit signal when the current exceeds a predetermined threshold. The current mirror circuit, coupled to a voltage source, the current sensor and the determination circuit, comprises a current mirror and a bypass path, delivers a mirrored current from the current mirror to the load upon receiving the short-circuit signal, and passes the current from the voltage source through the bypass path to the load in the absence of the short-circuit signal.