Patents by Inventor Beng Yee Teh

Beng Yee Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096095
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die to form a reconstituted wafer. A first insulating layer is formed over the reconstituted wafer. A first dummy opening is formed in the first insulating layer. A first conductive layer is formed on the first insulating layer including a first contact pad over the first dummy opening.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 20, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Peik Eng Ooi, Beng Yee Teh, Linda Pei Ee Chua
  • Publication number: 20250087545
    Abstract: A semiconductor device has a pre-molded discrete electrical component and a first encapsulant deposited over the pre-molded discrete electrical component. A first conductive layer is formed over the first encapsulant and pre-molded discrete electrical component. An electrical component is disposed over the first conductive layer. A second encapsulant is deposited over the electrical component and first conductive layer. A second conductive layer is formed over the second encapsulant. A conductive pillar is formed between the first conductive layer and second conductive layer through the second encapsulant. The pre-molded discrete electrical component has a discrete component and a third encapsulant deposited around the discrete component. The discrete component has an electrical terminal, a finish formed over the electrical terminal, and a third conductive layer formed over the finish.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 13, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Kai Chong Chan, Linda Pei Ee Chua, Yung Kuan Hsiao, Beng Yee Teh’, Jian Zuo, Yaojian Lin
  • Patent number: 8274145
    Abstract: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: September 25, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Leocadio M. Alabin, Librado Gatbonton, Chiu Hsieh Ong, Beng Yee Teh, Antonio B. Dimaano, Jr.
  • Publication number: 20090008768
    Abstract: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 8, 2009
    Inventors: Leocadio M. Alabin, Librado Gatbonton, Chiu Hsieh Ong, Beng Yee Teh, Antonio B. Dimaano, JR.