Abstract: A stored program controlled real time system includes a high-speed executive processor (29) which receives real time signals coming from an equipment (2) and which coacts parallel-synchronously with two substantially identical reserve processors (30, 31). The processors each contain a plurality of function units (3, 5, 6) mutually connected by a data bus (16). For indicating a faulty processor, the system includes a fault localizing means (32) which contains two comparators (34, 36), each of which has two inputs connected to the data buses of the three processors and its outputs connected to three fault indicators (42, 44, 46) each assigned to a processor. The executive processor (29) updates the reserve processors (30, 31) by means of two data transfer channels (33, 35), the inputs of which are connected to the data bus (20) of the executive processor and the outputs of which are connected to the data bus (19) of the respective reserve processors.

Abstract: A data processing system which includes an address bus connected to k computer elements is supervised with the aid of an arrangement including a plurality of indication registers connected to the bus and to an error signal generator. The address bus is capable of transferring 2n>k binary addresses. The indication registers are each accessed by its address transferred through the bus and each register stores an indication if its address is also assigned one of the computer elements. The generator generates an error signal on the reception of an indication that an address being transferred through the bus is not assigned a computer element.