Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter (12) is calibrated by a method that inserts a calibration test sequence into the D/A sub-converter. This is accomplished by forcing (SW) the comparators (COMP1-COMP7) of the A/D sub-converter to generate and insert the sequence into the D/A sub-converter.

Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter provides dynamic element matching. This is accomplished by forcing comparators of the A/D sub-converter to generate a scrambled thermometer code.

Abstract: An A/D converter calibration apparatus of the “skip-and-fill” type includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1, . . . , xN. The measured parameter are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds or falls below a predetermined change threshold. A calibration control signal CTRL_SKIP_RT is passed to a calibration control unit (104), which sets the background calibration skip rate to a high value if the measure exceeds the threshold an to a low value if it does not exceed the threshold.

Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter (12) is calibrated by a method that inserts a calibration test sequence into the D/A sub-converter. This is accomplished by forcing (SW) the comparators (COMP1-COMP7) of the A/D sub-converter to generate and insert the sequence into the D/A sub-converter.

Abstract: An A/D converter calibration apparatus includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1, . . . , xN. The measured parameters are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds a predetermined change threshold. When a change exceeding the threshold has been detected, a calibration trigger signal CAL_TRIG is passed to a calibration control unit (104), which initiates a background calibration sequence.

Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter (12) provides dynamic element matching. This is accomplished by forcing (24) the comparators (COMP1-COMP7) of the A/D sub-converter to generate a scrambled thermometer code.

Abstract: An A/D converter calibration apparatus of the “skip-and-fill” type includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1 . . . xN. The measured parameter are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds or falls below a predetermined change threshold. A calibration control signal CTRL_SKP_RT is passed to a calibration control unit (104), which sets the background calibration skip rate to a high value if the measure exceeds the threshold an to a low value if it does not exceed the threshold.

Abstract: An A/D converter calibration apparatus includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1, . . . , xN. The measured parameters are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds a predetermined change threshold. When a change exceeding the threshold has been detected, a calibration trigger signal CAL_TRIG is passed to a calibration control unit (104), which initiates a background calibration sequence.

Abstract: An A/D converter system includes a first A/D converter with calibration circuitry. Also included in the system is an auxiliary A/D converter having a lower performance level than the first A/D converter. Circuitry is provided for temporarily switching an A/D conversion from the first A/D converter to the auxiliary A/D converter during short time intervals used for calibration of the first A/D converter. The rate at which the A/D conversion is switched is lower than the sampling rate of the first A/D converter.

Abstract: A pipeline stage in a multi-bit/stage pipeline A/D converter is calibrated by switching a set of D/A converter unit-segments in the stage to predetermined states to produce a first digital signal. A second digital signal is produced by switching a predetermined unit-segment in the set to its complementary state and keeping the states of the other unit-segments in the set unchanged. The unit-segment is then associated with a calibration coefficient representing the deviation of the difference between the first and second digital signals from an expected difference between the first and second digital signals. This process is repeated for each unit-segment that is to be calibrated.

Abstract: A background calibrated A/D converter includes a random time interval generator that initiates background calibration at randomly selected time instants to increase the spurious-free dynamic range of the A/D converter.

Abstract: A method and apparatus for calibrating a pipeline stage in a multi-bit/stage pipeline A/D converter involves switching (S3, S4) a set of D/A converter unit-segments in the stage to predetermined states (+/−) for producing (S5) a first digital signal (d+), and switching (S6) a predetermined unit-segment in the set to its complementary state, keeping the states of the other unit-segments in said set unchanged, for producing (S7) a second digital signal (d−). The unit-segment is then associated (S8) with a calibration coefficient representing the deviation of the difference between the first and second digital signals from an expected difference between the first and second digital signals. This process is repeated for each unit-segment that is to be calibrated.

Abstract: An A/D converter system includes a regular A/D converter (10) with calibration means. Included is also a lower performance, as compared to the regular A/D converter, auxiliary A/D converter (20). Means (22, 24) are provided for temporarily switching, at a switching rate that is lower than the sampling rate of regular A/D converter (10), A/D conversion from the regular A/D converter (10) to the auxiliary A/D converter (20) during short time intervals used for calibration of the regular A/D converter (10).

Abstract: A background calibrated A/D converter includes a random time interval generator that initiates background calibration at randomly selected time instants to increase the spurious-free dynamic range of the A/D converter.

Abstract: Pipeline A/D-conversion of an analog input signal is performed according to a new and inventive algorithm which generates a Gray coded digital output signal. A pipeline A/D-converter comprises a number of cascaded stages through which the analog input signal is propagated. Each stage generally generates an output bit of the digital output signal, and furthermore processes the pipeline signal. According to the inventive Gray coding algorithm, the output bit generated in a stage determines whether or not the pipeline signal of that stage is inverted. In a pipeline A/D-converter based on the Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the inventive pipeline A/D-converter.

Abstract: Cyclic A/D-conversion of an analog input signal is performed according to a new and inventive recursive algorithm which generates a Gray coded digital output signal. In cyclic A/D-conversion, the output bits are generated cyclically, one by one. According to the inventive Gray coding algorithm, the analog input signal is cyclically subjected to a sample and hold operation, selectively, depending on the previously generated output bit, to a signal inversion, to an amplification by two, and to an addition of a predetermined reference signal. In a cyclic A/D-converter architecture based on the recursive Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the cyclic A/D-converter according to the invention.