Abstract: A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.

Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

Abstract: An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word.

Abstract: A soft decision value output detector includes a plurality of maximum a posteriori (MAP) detectors. The MAP detectors are configured to simultaneously generate state metrics for portions of a sampled data sequence, and to generate soft decision values based on the generated state metrics. Each of the MAP detectors includes a first MAP unit that generates state metrics by a reverse iteration using first and second reverse Viterbi operators and a forward iteration using a first forward Viterbi operator through portions of the sampled data sequence, and a second MAP unit that generates state metrics by a reverse iteration using third and fourth reverse Viterbi operators and a forward iteration using a second forward Viterbi operator through portions of the sampled data sequence.

Abstract: A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.

Abstract: A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.

Abstract: A soft decision value output detector includes a plurality of maximum a posteriori (MAP) detectors. The MAP detectors are connected in parallel, and configured to simultaneously generate state metrics for portions of a sampled data sequence, and to generate soft decision values based on the generated state metrics. The MAP detectors may generate soft decision values in a fixed latency manner and without buffering the sampled data sequence for a whole sector of a disk in a disk drive. The MAP detectors may generate soft decision values for portions of the sampled data sequence at least at a rate at which the portions of the sampled data sequence are input to the MAP detectors.

Abstract: In an I-F substitution loop having a summing junction for receiving both an I-F signal and a substitution signal, an amplification loop is connected in parallel with the substitution loop for amplifying and bandpass filtering the signal at the summing junction, and feeding back to the summing junction the processed summing junction signal, for reducing the phase noise at the summing junction.