Abstract: Power semiconductor devices, and more particularly arrangements of power semiconductor devices for improved thermal performance in high power applications are disclosed. Arrangements for multiple power semiconductor devices within a package and/or module are provided that more efficiently utilize the active device area of each power semiconductor device for a given operational specification. Certain arrangements are provided that reduce the effects of thermal crowding in order to provide increased power capability or a similar power capability in a reduced device size. Improved thermal balancing may be provided by variable spacing and/or variable offset distances between next-adjacent power semiconductor devices. In this manner, active areas of power devices and/or modules may include an increased density of power semiconductor devices within a given area while also exhibiting improved thermal profiles during operation, thereby providing improved operating characteristics and/or increased operating lifetimes.

Abstract: Power semiconductor devices, and more particularly arrangements of power semiconductor devices for improved thermal performance in high power applications are disclosed. Arrangements for multiple power semiconductor devices within a package and/or module are provided that more efficiently utilize the active device area of each power semiconductor device for a given operational specification. Certain arrangements are provided that reduce the effects of thermal crowding in order to provide increased power capability or a similar power capability in a reduced device size. Improved thermal balancing may be provided by variable spacing and/or variable offset distances between next-adjacent power semiconductor devices. In this manner, active areas of power devices and/or modules may include an increased density of power semiconductor devices within a given area while also exhibiting improved thermal profiles during operation, thereby providing improved operating characteristics and/or increased operating lifetimes.

Abstract: A module package can include a substrate; at least one device component configured to be positioned on the substrate; a module package lid configured to be positioned over the at least one device component and on the substrate, the module package lid exhibiting a plateau portion; and at least one mounting spring configured to be positioned on the module package lid, wherein the at least one mounting spring is configured to be mechanically coupled with a mounting surface and further positionally secure the module package lid and the at least one device component. Each mounting spring can include a middle portion; an end portion having a mounting hole; and a curved section between the middle portion and the end portion, the middle portion arranged to mate with the plateau portion of the module package lid when the end portion are secured to the substrate, the curved section being configured to prevent contact with a first corner portion of the module package lid.

Abstract: A module package can include a substrate; at least one device component configured to be positioned on the substrate; a module package lid configured to be positioned over the at least one device component and on the substrate, the module package lid exhibiting a plateau portion; and at least one mounting spring configured to be positioned on the module package lid, wherein the at least one mounting spring is configured to be mechanically coupled with a mounting surface and further positionally secure the module package lid and the at least one device component. Each mounting spring can include a middle portion; an end portion having a mounting hole; and a curved section between the middle portion and the end portion, the middle portion arranged to mate with the plateau portion of the module package lid when the end portion are secured to the substrate, the curved section being configured to prevent contact with a first corner portion of the module package lid.

Abstract: An RF package includes a substrate mountable on a base plate, a non-conductive cover overlying the substrate, and quasi-serpentine stepped source leads attached to an upper surface of the substrate and extending from at least one of a pair of opposite sides of the upper surface of the substrate to tapered lower surfaces of the cover. The cover includes a recess to receive the substrate. The recess includes stress distribution surface areas to engage and press outer edge portions of opposite sides of the substrate against a base plate or heat sink. The tapered lower surfaces of the cover engage with and press against the stepped source leads when securing the RF package to the base plate or heat sink using one or more fasteners or bolts. The cover includes structural features to improve preferential deformation when a mounting force is applied.

Abstract: A method for producing a multi-layer thick-film RF package includes forming conductive layer(s) including one or more source portions, one or more gate portions, and/or one or more drain portions on a ceramic substrate. The conductive layer(s) and the ceramic substrate are fired or otherwise heated in a furnace until sintered. Thereafter, a dielectric pattern is formed on the conductive layer(s) and fired or otherwise heated in the furnace until sintered. Then, a conductive bridge is formed on the dielectric pattern, over the one or more drain portions and between the one or more source portions, which is then fired until sintered in the furnace. As a result, a monolithic, single-piece, sintered, high-frequency RF power transistor package having circuit features including a highly conductive and low capacitive bridge is produced.

Abstract: A method for producing a multi-layer thick-film RF package includes forming conductive layer(s) including one or more source portions, one or more gate portions, and/or one or more drain portions on a ceramic substrate. The conductive layer(s) and the ceramic substrate are fired or otherwise heated in a furnace until sintered. Thereafter, a dielectric pattern is formed on the conductive layer(s) and fired or otherwise heated in the furnace until sintered. Then, a conductive bridge is formed on the dielectric pattern, over the one or more drain portions and between the one or more source portions, which is then fired until sintered in the furnace. As a result, a monolithic, single-piece, sintered, high-frequency RF power transistor package having circuit features including a highly conductive and low capacitive bridge is produced.

Abstract: An RF package includes a substrate mountable on a base plate, a non-conductive cover overlying the substrate, and quasi-serpentine stepped source leads attached to an upper surface of the substrate and extending from at least one of a pair of opposite sides of the upper surface of the substrate to tapered lower surfaces of the cover. The cover includes a recess to receive the substrate. The recess includes stress distribution surface areas to engage and press outer edge portions of opposite sides of the substrate against a base plate or heat sink. The tapered lower surfaces of the cover engage with and press against the stepped source leads when securing the RF package to the base plate or heat sink using one or more fasteners or bolts. The cover includes structural features to improve preferential deformation when a mounting force is applied.