Abstract: An apparatus (100) comprising a programmable memory transfer request processing (PMTRP) unit (120) and a programmable direct memory access (PDMA) unit (140). The PMTRP unit (120) comprises at least one programmable region descriptor (123). The PDMA unit (140) comprises at least one programmable memory-to-memory transfer control descriptor (148, 149, 150). The PDMA unit (140) is adapted to send (143) a memory transfer request to the PMTRP unit (120). The PMTRP unit (120) is adapted to receive (134) and successfully process a memory transfer request issued by the PDMA unit (120) that is addressed to a memory location that is associated with a portion of at least one of the at least one region descriptor (123) of the PMTRP unit (120).

Abstract: A shared memory computing device optimised for executing realtime software that has at least one interconnect master, a shared memory, N cache modules and M processor cores, where the value of N>=1 and M =N. Each of the N cache modules has a means to implement an update-type cache coherency policy across those N cache modules. Each processor core is assigned a different one of the N cache modules as that processor core's private cache. Furthermore, the memory transfer request latency of non-atomic memory transfer requests issued by each of the M processor cores to the shared memory is not modified by: (a) the memory transfer requests issued by any of the other M processor cores; or (b) the memory transfer requests issued by at least one other interconnect master.

Abstract: An apparatus (100) comprising a programmable memory transfer request processing (PMTRP) unit (120) and a programmable direct memory access (PDMA) unit (140). The PMTRP unit (120) comprises at least one programmable region descriptor (123). The PDMA unit (140) comprises at least one programmable memory-to-memory transfer control descriptor (148, 149, 150). The PDMA unit (140) is adapted to send (143) a memory transfer request to the PMTRP unit (120). The PMTRP unit (120) is adapted to receive (134) and successfully process a memory transfer request issued by the PDMA unit (120) that is addressed to a memory location that is associated with a portion of at least one of the at least one region descriptor (123) of the PMTRP unit (120).

Abstract: A shared memory computing architecture (300) has M interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with T timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with R timeslots. For each of the R timeslots, that timeslot: corresponds to one memory transfer request timeslot and starts at least L clock cycles after the start time of that corresponding memory request timeslot. The value of L is >=3 and <T. Interconnect target (370) is connected to interconnect (319). Each interconnect master (350, 351, 352, 353, 354) is connected to interconnect (319).

Abstract: A shared memory computing device that has a system interconnect, an on-chip random access memory (RAM), at least one sub-computing device and a peripheral. The RAM is connected to the system interconnect. Each sub-computing device has: (a) a first local interconnect, (b) an interconnect master connected to a local interconnect of the sub-computing device; and (c) an interconnect bridge; in which the interconnect master is adapted to issue memory transfer requests to the RAM over that bridge. The peripheral comprises a target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; and a first interconnect master port which is adapted to issue memory transfer requests to the RAM. The interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.

Abstract: A bidirectional interconnect for transporting memory transfer requests and their corresponding memory transfer responses that has: (a) a unidirectional interconnect to transport memory transfer requests; and (b) a unidirectional interconnect to transport memory transfer responses. The write memory transfer responses include at least a copy of the data to be written of the corresponding write memory transfer request. The memory transfer responses may also include a copy of the corresponding memory transfer request. This interconnect is particularly well suited for use in cache-coherent real-time computing architectures that have peripherals.

Abstract: A shared memory computing device optimised for worst case execution time analysis that has at least one interconnect master, N cache modules and N processor cores. Each cache module has a finite state machine that employs an update-type cache coherency policy. Each processor core is assigned a different one of the N fully associative cache modules as its private cache. Furthermore, the execution time of memory transfer requests issued by each of the N processor cores is not modified by: (a) the unrelated memory transfer requests issued by any of the other N processor cores; or (b) the unrelated memory transfer requests issued by at least one other interconnect master.

Abstract: A shared memory computing architecture (300) has M interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with T timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with R timeslots. For each of the R timeslots, that timeslot: corresponds to one memory transfer request timeslot and starts at least L clock cycles after the start time of that corresponding memory request timeslot. The value of L is >=3 and <T. Interconnect target (370) is connected to interconnect (319). Each interconnect master (350, 351, 352, 353, 354) is connected to interconnect (319).

Abstract: Apparatus for encoding and deciphering inter-chip signals has a single pseudo-random number generator (PRNG) (31, 41, 42) which generates a single pseudo-random number stream. A decision making module (32, 43) creates two pseudo-random number streams from the output of the PRNG (31, 41, 42). Buffers (33, 35, 37, 44, 45) buffer pseudo-random number streams.