Patents by Inventor Benjamin Beker

Benjamin Beker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240203736
    Abstract: A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: GABRIEL H. LOH, TODD DAVID BASSO, STEVEN TU, JOSHUA A. HORT, CHIA-KEN LEONG, BENJAMIN BEKER, ANWAR P. KASHEM
  • Publication number: 20120105129
    Abstract: A power gating apparatus includes an integrated circuit package with a first voltage reference plane and a second voltage reference plane, and an integrated circuit that includes a circuit block, and a switch block. The first and second voltage reference planes may be electrically isolated from one another. The switch block may include a plurality of switches arranged in a ring surrounding the circuit block. The first voltage reference plane may be electrically coupled between an external voltage reference and the plurality of switches, and the second voltage reference plane may be electrically coupled between the plurality of switches and the circuit block. The second voltage reference plane may also distribute an electric current throughout the circuit block. In addition, each of the switches is configured to interrupt an electrical path between the first reference voltage plane and the circuit block in response to a control signal.
    Type: Application
    Filed: October 28, 2010
    Publication date: May 3, 2012
    Inventors: Samuel D. Naffziger, Bruce Gieseke, Benjamin Beker
  • Publication number: 20100237462
    Abstract: Various semiconductor chip carrier substrate circuit tuning apparatus and methods are disclosed. In one aspect, a method of manufacturing is provided that includes assembling a semiconductor chip carrier substrate with a first input/output site adapted to electrically connect to an external component and a second input/output site adapted to electrically connect to an input/output site of a semiconductor chip. An inductor is placed in the semiconductor chip carrier substrate. The inductor is electrically connected between the first and second input/output sites. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site due to coupling to a second conductor in the semiconductor chip carrier substrate.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Inventors: Benjamin Beker, James Foppiano
  • Patent number: 7692467
    Abstract: Capacitive decoupling circuits and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip with a first power rail for a first no-load bias level and a ground rail. A first voltage divider is electrically coupled between the first power rail and the ground rail and has a midpoint node. A first pair of capacitors is electrically coupled between the first power rail, the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail. A second power rail has a second no-load bias less than the first no-load bias. A second pair of capacitors is electrically coupled between the ground rail and the second power rail to provide capacitive decoupling for power delivered to the second power rail.
    Type: Grant
    Filed: February 3, 2007
    Date of Patent: April 6, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Benjamin Beker
  • Publication number: 20080186649
    Abstract: Capacitive decoupling circuits and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip with a first power rail for a first no-load bias level and a ground rail. A first voltage divider is electrically coupled between the first power rail and the ground rail and has a midpoint node. A first pair of capacitors is electrically coupled between the first power rail, the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail. A second power rail has a second no-load bias less than the first no-load bias. A second pair of capacitors is electrically coupled between the ground rail and the second power rail to provide capacitive decoupling for power delivered to the second power rail.
    Type: Application
    Filed: February 3, 2007
    Publication date: August 7, 2008
    Inventor: Benjamin Beker
  • Publication number: 20080186650
    Abstract: Decoupling capacitors and methods of manufacturing the same are provided. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip and providing a capacitor stack for the semiconductor chip. The capacitor stack includes a first group of terminations and a second group of terminations. A first group of electrodes is included that have terminals coupled to the first group of terminations and a second group of electrodes is included that have terminals coupled to the second group of terminations. At least one electrode of the first group of electrodes has at least one less terminal than the number of terminations in the first group of terminations in order to provide the capacitor stack with a known equivalent series resistance. The capacitor stack is electrically coupled to the semiconductor chip.
    Type: Application
    Filed: February 3, 2007
    Publication date: August 7, 2008
    Inventors: Benjamin Beker, Eric Tosaya
  • Patent number: 6859115
    Abstract: A computer power supply system for reducing the AC impedance of a DC power supply (52) at inputs pins of a computing device (54) such as a processor. A quarter wavelength transmission line stub (58) is connected to a computing device DC power supply input pin. The stub is open circuited at its end opposite the pin. The wavelength is selected to match a frequency at which power supply impedance is known to be high. The stub appears as a low impedance at the selected frequency. Multiple stubs at different frequencies may be used to provide reduced impedance over a broader frequency band. Stubs may be formed from printed circuit board traces on a motherboard of from metalization patterns on a computing device package.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: February 22, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tom J. Hirsch, Benjamin Beker