Abstract: Systems, devices, and methods for deploying a graft to a treatment site of a patient. Exemplary systems include a device body and an insertion mechanism. The device body can have a handle, a trigger, and a controller. The insertion mechanism can be in operative association with the device body, and can have an outer sheath, a support shaft disposed at least partially within the outer sheath, an expansion mechanism coupled with the support shaft, and a graft in contact with the expansion mechanism.

Abstract: Techniques and/or systems are disclosed for an implement attachment assembly for a work vehicle. The implement attachment assembly includes a member having a body extending longitudinally between a first end and a second end. The first end includes a central axis disposed at a first height relative to a member vertical axis and the second end includes a central axis disposed at a second height relative to the member vertical axis. The first end central axis is operably disposed at a different height than the second end central axis. The first end is configured to operably connect to the work vehicle. The second end is configured to operably connect to a coupling device.

Abstract: A system and method of improved performant content source crawling. A content source crawling technology that is performant and focused on an initial rapid crawling of a content source to find specific file signatures so that it can determine an inventory of files that have been modified since the last full index event, thereby minimizing the time and computing resources necessary to perform a full crawl on just the select files to update to the search index. A method of Signature Flagging is disclosed and is used to selectively crawl the metadata about contained files and folders found within a content source in order to create that information in an Index within the Shinydocs Search Library.

Abstract: Devices and methods for fusing a sacroiliac joint of a patient. Exemplary fusion systems include an implant body and one or more screws. An implant body can have a medial side configured to engage a sacrum of a patient, a lateral side configured to engage an ilium of the patient, a distal portion, and a proximal portion having an opening configured to receive a screw. A screw can include a distal portion having a threaded portion configured to engage bone of the patient, and a proximal portion configured engage the opening in the proximal portion of the implant body.

Abstract: A track tension system including a hydraulic cylinder coupled between a drive frame and idler of a track system, an accumulator and a hydraulic valve that controls flow between the cylinder and accumulator. The cylinder extends and retracts to change the distance between the drive frame and idler which increases and decreases, respectively, tension on the track system. The hydraulic valve can be opened to allow flow between the cylinder and accumulator, and closed to block flow between the cylinder and accumulator. Control factors can be monitored to control valve position. An overload pressure relief can allow flow between the cylinder and accumulator when the hydraulic valve is closed and pressure in the cylinder reaches overload pressure. An orifice can allow constricted flow between the cylinder and accumulator when the hydraulic valve is closed. A check valve can connect the track tension system to a vehicle hydraulic system.

Abstract: Apparatus and methods for providing spinal percutaneous delivery of an implant that can rigidly fixate the spinous process of a first superior bone and a second inferior bone of a functional spinal unit. In one aspect, the device comprises two bone abutment members connected via an interconnecting member. In another aspect, the method comprises implanting at least two spinal implant apparatus within a target disc space via an implantation apparatus. In another aspect, a placement instrument comprising an implant delivery segment, an anchor segment, and an articulating arm is disclosed.

Abstract: A system includes a log receiving module, an authentication graph module, a sampling module, an embedding module, a training module, a link prediction module, and an anomaly detection module. The log receiving module is configured to receive a first plurality of network-level authentication logs. The authentication graph module is configured to generate an authentication graph. The sampling module is configured to generate a plurality of sequences. The embedding module is configured to tune a plurality of node embeddings according to the plurality of sequences. The training module is configured to train a link predictor according to the plurality of node embeddings and ground-truth edge information from the authentication graph. The link prediction module is configured to apply the link predictor to performs a link prediction. The anomaly detection module is configured to perform anomaly detection according to the link prediction.

Abstract: The present invention concerns selective renal denervation treatment of drug resistant hypertensive patients by correlating the patients’ genetic panel by categorization and hierarchy according to patients’ genetic variants within the functional genes for heart activity, for the renin-angiotensin aldosterone system, and for renal activity.

Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry.

Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.

Abstract: Disclosed embodiments relate to controlling sets of graphics work (e.g., kicks) assigned to graphics processor circuitry. In some embodiments, tracking slot circuitry implements entries for multiple tracking slots. Slot manager circuitry may store, using an entry of the tracking slot circuitry, software-specified information for a set of graphics work, where the information includes: type of work, dependencies on other sets of graphics work, and location of data for the set of graphics work. The slot manager circuitry may prefetch, from the location and prior to allocating shader core resources for the set of graphics work, configuration register data for the set of graphics work. Control circuitry may program configuration registers for the set of graphics work using the prefetched data and initiate processing of the set of graphics work by the graphics processor circuitry according to the dependencies. Disclosed techniques may reduce kick-to-kick transition time, in some embodiments.

Abstract: Disclosed techniques relate to work distribution in graphics processors. In some embodiments, an apparatus includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. The circuitry may determine different distribution rules for first and second sets of graphics work and map logical slots to distributed hardware slots based on the distribution rules. In various embodiments, disclosed techniques may advantageously distribute work efficiently across distributed shader processors for graphics kicks of various sizes.

Abstract: Techniques are disclosed relating to affinity-based scheduling of graphics work. In disclosed embodiments, first and second groups of graphics processor sub-units may share respective first and second caches. Distribution circuitry may receive a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units. The distribution circuitry may assign subsets of the set of graphics work based on the mapping. This may improve cache efficiency, in some embodiments, by allowing graphics work that accesses the same memory areas to be assigned to the same group of sub-units that share a cache.

Abstract: Techniques are disclosed relating to dynamically adjusting buffering for distributing compute work in a graphics processor. In some embodiments, the graphics processor includes shader circuitry configured to process compute work from a compute kernel, multiple distributed workload parser circuits configured to send compute work to the shader circuitry, primary workload parser circuitry configured to send, via a communications fabric, compute work from the compute kernel to the distributed workload parser circuits, and buffer circuitry configured to buffer compute work received by one or more of the distributed workload parser circuits from the primary workload parser circuitry. In some embodiments, the graphics processor is configured to dynamically adjust a limit on the number of entries used in the buffer circuitry based on information indicating complexity of the compute kernel. This may advantageously maintain launch rates while reducing or avoiding workload imbalances, in some embodiments.

Abstract: There are provided systems and methods for authentication depending on device capabilities and user requests based on situational information collected in advance of a device becoming non-operational. A user may wish to utilize some device process, such as access and use of a device application or other module. For example, a user may wish to utilize a payment application of the communication device, or authenticate the user using a service provider accessible through the communication device. If the communication device becomes non-operational (e.g., lack of power or signal strength), the user may be prevented from authenticating through the communication device. Thus, the user may establish a limited use authentication credential from situational data to the user and device (e.g., location or current image) that allows the user to authenticate with the service provider. The authentication credential may be limited to a location, amount, and/or type of authentication.

Abstract: Techniques are disclosed relating to dynamically adjusting buffering for distributing compute work in a graphics processor. In some embodiments, the graphics processor includes shader circuitry configured to process compute work from a compute kernel, multiple distributed workload parser circuits configured to send compute work to the shader circuitry, primary workload parser circuitry configured to send, via a communications fabric, compute work from the compute kernel to the distributed workload parser circuits, and buffer circuitry configured to buffer compute work received by one or more of the distributed workload parser circuits from the primary workload parser circuitry. In some embodiments, the graphics processor is configured to dynamically adjust a limit on the number of entries used in the buffer circuitry based on information indicating complexity of the compute kernel. This may advantageously maintain launch rates while reducing or avoiding workload imbalances, in some embodiments.

Abstract: The graph-based source code vulnerability detection system that uses a code-similarity style technique to identify highly modified vulnerable code clones while remaining generic to all vulnerability types. The system abstracts vulnerabilities in source code to the graph domain, allowing it to identify key relationships between textual elements that are not directly discernible from the text alone. Additionally, the system analyzes the patched code in addition to the vulnerable code to identify specific relationships in the graph that are tied directly to the vulnerable code segment, the patched code segment, and the contextual code of a particular vulnerability. By separating the vulnerability representation into these three components, a matching algorithm identifies vulnerable code clones while tolerating modifications at each level independently, providing more robust detection of modified vulnerable code clones.

Abstract: A system includes a log receiving module, an authentication graph module, a sampling module, an embedding module, a training module, a link prediction module, and an anomaly detection module. The log receiving module is configured to receive a first plurality of network-level authentication logs. The authentication graph module is configured to generate an authentication graph. The sampling module is configured to generate a plurality of sequences. The embedding module is configured to tune a plurality of node embeddings according to the plurality of sequences. The training module is configured to train a link predictor according to the plurality of node embeddings and ground-truth edge information from the authentication graph. The link prediction module is configured to apply the link predictor to performs a link prediction. The anomaly detection module is configured to perform anomaly detection according to the link prediction.

Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.

Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.