Patents by Inventor Benjamin Bowman
Benjamin Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12351873Abstract: The present invention concerns selective renal denervation treatment of drug resistant hypertensive patients by correlating the patients' genetic panel by categorization and hierarchy according to patients' genetic variants within the functional genes for heart activity, for the renin-angiotensin aldosterone system, and for renal activity.Type: GrantFiled: December 21, 2018Date of Patent: July 8, 2025Assignee: Geneticure Inc.Inventors: Eric Snyder, Ryan Sprissler, Benjamin Bowman, Scott C. Snyder
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Patent number: 12333339Abstract: Techniques are disclosed relating to affinity-based scheduling of graphics work. In disclosed embodiments, first and second groups of graphics processor sub-units may share respective first and second caches. Distribution circuitry may receive a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units. The distribution circuitry may assign subsets of the set of graphics work based on the mapping. This may improve cache efficiency, in some embodiments, by allowing graphics work that accesses the same memory areas to be assigned to the same group of sub-units that share a cache.Type: GrantFiled: August 11, 2021Date of Patent: June 17, 2025Assignee: Apple Inc.Inventors: Andrew M. Havlir, Ajay Simha Modugala, Benjamin Bowman, Yunjun Zhang
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Patent number: 12265844Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry.Type: GrantFiled: September 7, 2021Date of Patent: April 1, 2025Assignee: Apple Inc.Inventors: Benjamin Bowman, Fergus W. MacGarry, Kutty Banerjee, Pratik Chandresh Shah
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Patent number: 12190164Abstract: Disclosed embodiments relate to controlling sets of graphics work (e.g., kicks) assigned to graphics processor circuitry. In some embodiments, tracking slot circuitry implements entries for multiple tracking slots. Slot manager circuitry may store, using an entry of the tracking slot circuitry, software-specified information for a set of graphics work, where the information includes: type of work, dependencies on other sets of graphics work, and location of data for the set of graphics work. The slot manager circuitry may prefetch, from the location and prior to allocating shader core resources for the set of graphics work, configuration register data for the set of graphics work. Control circuitry may program configuration registers for the set of graphics work using the prefetched data and initiate processing of the set of graphics work by the graphics processor circuitry according to the dependencies. Disclosed techniques may reduce kick-to-kick transition time, in some embodiments.Type: GrantFiled: August 11, 2021Date of Patent: January 7, 2025Assignee: Apple Inc.Inventors: Steven Fishwick, Fergus W. MacGarry, Jonathan M. Redshaw, David A. Gotwalt, Ali Rabbani Rankouhi, Benjamin Bowman
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Patent number: 12086644Abstract: Disclosed techniques relate to work distribution in graphics processors. In some embodiments, an apparatus includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. The circuitry may determine different distribution rules for first and second sets of graphics work and map logical slots to distributed hardware slots based on the distribution rules. In various embodiments, disclosed techniques may advantageously distribute work efficiently across distributed shader processors for graphics kicks of various sizes.Type: GrantFiled: August 11, 2021Date of Patent: September 10, 2024Assignee: Apple Inc.Inventors: Andrew M. Havlir, Steven Fishwick, David A. Gotwalt, Benjamin Bowman, Ralph C. Taylor, Melissa L. Velez, Mladen Wilder, Ali Rabbani Rankouhi, Fergus W. MacGarry
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Publication number: 20240272940Abstract: Disclosed techniques relate to scheduling sets of graphics work with dependencies. In some embodiments, a first set of graphics work depends on a second set of graphics work. Control circuitry may, in response to a release signal that indicates the second set reaching a first processing point, initiate processing of the first set. Control circuitry may, in response to reaching a kick gate point, stall processing of the first set. Control circuitry may, in response to an end signal for the second set, resume processing of the first set.Type: ApplicationFiled: August 16, 2023Publication date: August 15, 2024Inventors: Benjamin Bowman, Ali Rabbani Rankouhi, Jonathan M. Redshaw, Steven Fishwick
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Patent number: 12039368Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.Type: GrantFiled: September 7, 2021Date of Patent: July 16, 2024Assignee: Apple Inc.Inventors: Benjamin Bowman, Fergus W. MacGarry, Kutty Banerjee, Pratik Chandresh Shah
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Patent number: 11856013Abstract: A system includes a log receiving module, an authentication graph module, a sampling module, an embedding module, a training module, a link prediction module, and an anomaly detection module. The log receiving module is configured to receive a first plurality of network-level authentication logs. The authentication graph module is configured to generate an authentication graph. The sampling module is configured to generate a plurality of sequences. The embedding module is configured to tune a plurality of node embeddings according to the plurality of sequences. The training module is configured to train a link predictor according to the plurality of node embeddings and ground-truth edge information from the authentication graph. The link prediction module is configured to apply the link predictor to performs a link prediction. The anomaly detection module is configured to perform anomaly detection according to the link prediction.Type: GrantFiled: June 29, 2020Date of Patent: December 26, 2023Assignee: The George Washington UniversityInventors: Benjamin Bowman, Craig Laprade, H. Howie Huang
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Publication number: 20230203582Abstract: The present invention concerns selective renal denervation treatment of drug resistant hypertensive patients by correlating the patients’ genetic panel by categorization and hierarchy according to patients’ genetic variants within the functional genes for heart activity, for the renin-angiotensin aldosterone system, and for renal activity.Type: ApplicationFiled: December 21, 2018Publication date: June 29, 2023Inventors: Eric Snyder, Ryan Sprissler, Benjamin Bowman, Scott C. Snyder
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Publication number: 20230077058Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Benjamin Bowman, Fergus W. MacGarry, Kutty Banerjee, Pratik Chandresh Shah
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Publication number: 20230075531Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Benjamin Bowman, Fergus W. MacGarry, Kutty Banerjee, Pratik Chandresh Shah
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Publication number: 20230048951Abstract: Disclosed embodiments relate to controlling sets of graphics work (e.g., kicks) assigned to graphics processor circuitry. In some embodiments, tracking slot circuitry implements entries for multiple tracking slots. Slot manager circuitry may store, using an entry of the tracking slot circuitry, software-specified information for a set of graphics work, where the information includes: type of work, dependencies on other sets of graphics work, and location of data for the set of graphics work. The slot manager circuitry may prefetch, from the location and prior to allocating shader core resources for the set of graphics work, configuration register data for the set of graphics work. Control circuitry may program configuration registers for the set of graphics work using the prefetched data and initiate processing of the set of graphics work by the graphics processor circuitry according to the dependencies. Disclosed techniques may reduce kick-to-kick transition time, in some embodiments.Type: ApplicationFiled: August 11, 2021Publication date: February 16, 2023Inventors: Steven Fishwick, Fergus W. MacGarry, Jonathan M. Redshaw, David A. Gotwalt, Ali Rabbani Rankouhi, Benjamin Bowman
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Publication number: 20230047481Abstract: Techniques are disclosed relating to affinity-based scheduling of graphics work. In disclosed embodiments, first and second groups of graphics processor sub-units may share respective first and second caches. Distribution circuitry may receive a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units. The distribution circuitry may assign subsets of the set of graphics work based on the mapping. This may improve cache efficiency, in some embodiments, by allowing graphics work that accesses the same memory areas to be assigned to the same group of sub-units that share a cache.Type: ApplicationFiled: August 11, 2021Publication date: February 16, 2023Inventors: Andrew M. Havlir, Ajay Simha Modugala, Benjamin Bowman, Yunjun Zhang
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Publication number: 20230050061Abstract: Disclosed techniques relate to work distribution in graphics processors. In some embodiments, an apparatus includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. The circuitry may determine different distribution rules for first and second sets of graphics work and map logical slots to distributed hardware slots based on the distribution rules. In various embodiments, disclosed techniques may advantageously distribute work efficiently across distributed shader processors for graphics kicks of various sizes.Type: ApplicationFiled: August 11, 2021Publication date: February 16, 2023Inventors: Andrew M. Havlir, Steven Fishwick, David A. Gotwalt, Benjamin Bowman, Ralph C. Taylor, Melissa L. Velez, Mladen Wilder, Ali Rabbani Rankouhi, Fergus W. MacGarry
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Patent number: 11500692Abstract: Techniques are disclosed relating to dynamically adjusting buffering for distributing compute work in a graphics processor. In some embodiments, the graphics processor includes shader circuitry configured to process compute work from a compute kernel, multiple distributed workload parser circuits configured to send compute work to the shader circuitry, primary workload parser circuitry configured to send, via a communications fabric, compute work from the compute kernel to the distributed workload parser circuits, and buffer circuitry configured to buffer compute work received by one or more of the distributed workload parser circuits from the primary workload parser circuitry. In some embodiments, the graphics processor is configured to dynamically adjust a limit on the number of entries used in the buffer circuitry based on information indicating complexity of the compute kernel. This may advantageously maintain launch rates while reducing or avoiding workload imbalances, in some embodiments.Type: GrantFiled: September 15, 2020Date of Patent: November 15, 2022Assignee: Apple Inc.Inventors: Andrew M. Havlir, Benjamin Bowman
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Patent number: 11488139Abstract: There are provided systems and methods for authentication depending on device capabilities and user requests based on situational information collected in advance of a device becoming non-operational. A user may wish to utilize some device process, such as access and use of a device application or other module. For example, a user may wish to utilize a payment application of the communication device, or authenticate the user using a service provider accessible through the communication device. If the communication device becomes non-operational (e.g., lack of power or signal strength), the user may be prevented from authenticating through the communication device. Thus, the user may establish a limited use authentication credential from situational data to the user and device (e.g., location or current image) that allows the user to authenticate with the service provider. The authentication credential may be limited to a location, amount, and/or type of authentication.Type: GrantFiled: May 28, 2019Date of Patent: November 1, 2022Assignee: PAYPAL, INC.Inventors: Billy Henry Runyan, Marty Jorgensen, Mohammad Zunaid Siddique, Rahul Nair, Eduardo Batlle, Michael Benjamin Bowman, Rashmi Singh Prakash
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Publication number: 20220083396Abstract: Techniques are disclosed relating to dynamically adjusting buffering for distributing compute work in a graphics processor. In some embodiments, the graphics processor includes shader circuitry configured to process compute work from a compute kernel, multiple distributed workload parser circuits configured to send compute work to the shader circuitry, primary workload parser circuitry configured to send, via a communications fabric, compute work from the compute kernel to the distributed workload parser circuits, and buffer circuitry configured to buffer compute work received by one or more of the distributed workload parser circuits from the primary workload parser circuitry. In some embodiments, the graphics processor is configured to dynamically adjust a limit on the number of entries used in the buffer circuitry based on information indicating complexity of the compute kernel. This may advantageously maintain launch rates while reducing or avoiding workload imbalances, in some embodiments.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Inventors: Andrew M. Havlir, Benjamin Bowman
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Publication number: 20210279338Abstract: The graph-based source code vulnerability detection system that uses a code-similarity style technique to identify highly modified vulnerable code clones while remaining generic to all vulnerability types. The system abstracts vulnerabilities in source code to the graph domain, allowing it to identify key relationships between textual elements that are not directly discernible from the text alone. Additionally, the system analyzes the patched code in addition to the vulnerable code to identify specific relationships in the graph that are tied directly to the vulnerable code segment, the patched code segment, and the contextual code of a particular vulnerability. By separating the vulnerability representation into these three components, a matching algorithm identifies vulnerable code clones while tolerating modifications at each level independently, providing more robust detection of modified vulnerable code clones.Type: ApplicationFiled: March 4, 2021Publication date: September 9, 2021Inventors: Benjamin Bowman, H. Howie Huang
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Publication number: 20210243212Abstract: A system includes a log receiving module, an authentication graph module, a sampling module, an embedding module, a training module, a link prediction module, and an anomaly detection module. The log receiving module is configured to receive a first plurality of network-level authentication logs. The authentication graph module is configured to generate an authentication graph. The sampling module is configured to generate a plurality of sequences. The embedding module is configured to tune a plurality of node embeddings according to the plurality of sequences. The training module is configured to train a link predictor according to the plurality of node embeddings and ground-truth edge information from the authentication graph. The link prediction module is configured to apply the link predictor to performs a link prediction. The anomaly detection module is configured to perform anomaly detection according to the link prediction.Type: ApplicationFiled: June 29, 2020Publication date: August 5, 2021Inventors: Benjamin BOWMAN, Craig LAPRADE, H. Howie Huang
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Patent number: 10795730Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.Type: GrantFiled: September 28, 2018Date of Patent: October 6, 2020Assignee: Apple Inc.Inventors: Kutty Banerjee, Benjamin Bowman, Terence M. Potter, Tatsuya Iwamoto, Gokhan Avkarogullari