Abstract: A non-zero caster angle for the rear axle swivel caster wheels on a self-propelled agricultural harvesting machine wherein steering is accomplished by varying speed and/or direction of forward drive wheels. The non-zero caster angle may be fixed or an adjuster mechanism may be provided to allow adjustment within a range of caster angles. The adjuster mechanism incorporates a fixed portion connected to the tractor frame and a pair of rotating portions, one connected to each caster wheel which allows rotation of the caster axis in a plane parallel to the machine longitudinal axis. Also disclosed is an actuator mechanism for providing powered adjustment of the caster angle, even including a control system for active caster angle adjustment.

Abstract: A non-zero caster angle for the rear axle swivel caster wheels on a self-propelled agricultural harvesting machine wherein steering is accomplished by varying speed and/or direction of forward drive wheels. The non-zero caster angle may be fixed or an adjuster mechanism may be provided to allow adjustment within a range of caster angles. The adjuster mechanism incorporates a fixed portion connected to the tractor frame and a pair of rotating portions, one connected to each caster wheel which allows rotation of the caster axis in a plane parallel to the machine longitudinal axis. Also disclosed is an actuator mechanism for providing powered adjustment of the caster angle, even including a control system for active caster angle adjustment.

Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).

Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).