Abstract: Examples described herein relate to a circuit board that includes a device, firmware memory, and a power controller. In some examples, the firmware memory is to store a firmware update and in response to a software-initiated command, the power controller is to reduce power to the device to cause a firmware update of the device and restore power to the device to cause execution of the firmware update. In some examples, the power controller is to reduce power solely to the device independent from power supply to at least one other device. In some examples, device configuration is saved prior to reduction of power to the device and restored to the device after power is restored to the device.

Abstract: Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

Abstract: An adaptor is described. The adaptor includes a first interface. The first interface is designed to support traffic and command flows to multiple transceivers through a single instance of the first interface. The adaptor includes multiple interfaces on a transceiver side. The multiple interfaces are to mate to respective transceivers. The multiple interfaces are different than the first interface, wherein the first interface is a QSFP interface and the multiple interfaces are SFP interfaces. The adaptor includes a flex cable between the first interface and the multiple interfaces. The adaptor includes electronic circuitry to translate QSFP commands received at the first interface into SFP commands presented to the respective transceivers through the multiple interfaces.

Abstract: An I/O controller includes a port to couple to a network, a buffer to buffer network data, and an interface to support a link to couple the I/O controller to another device. The I/O controller monitors a buffer to determine an amount of traffic on the port, initiates, at the interface, a power management transition on the link based on the amount of traffic, and mitigate latency associated with the power management transition at the port.

Abstract: Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

Abstract: Examples described herein relate to a circuit board that includes a device, firmware memory, and a power controller. In some examples, the firmware memory is to store a firmware update and in response to a software-initiated command, the power controller is to reduce power to the device to cause a firmware update of the device and restore power to the device to cause execution of the firmware update. In some examples, the power controller is to reduce power solely to the device independent from power supply to at least one other device. In some examples, device configuration is saved prior to reduction of power to the device and restored to the device after power is restored to the device.