Patents by Inventor Benjamin Cutler
Benjamin Cutler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7548996Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: September 12, 2005Date of Patent: June 16, 2009Assignees: Hitachi, Ltd., Equator Technologies, Inc.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, John Poole, legal representative, Ashok Raman, Eric Rehm, Radhika Thekkath, David Poole
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Patent number: 7457890Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: GrantFiled: October 30, 2006Date of Patent: November 25, 2008Assignee: Hitachi, Ltd.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 7272670Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.Type: GrantFiled: February 5, 2001Date of Patent: September 18, 2007Assignee: HitachiInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20070130401Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: ApplicationFiled: October 30, 2006Publication date: June 7, 2007Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20060288134Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: ApplicationFiled: September 12, 2005Publication date: December 21, 2006Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath, John Poole
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Patent number: 7051123Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: November 10, 2000Date of Patent: May 23, 2006Assignees: Hitachi, Ltd., Equator Technologies, Inc.,Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, Ashok Raman, Eric Rehm, Radhika Thekkath
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Publication number: 20040255058Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: June 15, 2004Publication date: December 16, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20040221071Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: February 5, 2001Publication date: November 4, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 6702295Abstract: A dynamic seal assembly has an outer carrier member formed of one-piece having an outer flange, an inner flange, and an intermediate portion presenting first and second shoulders. A PTFE seal member is disposed about the second shoulder and is compressed axially by a case member which, while the PTFE seal is compressed, is staked to the carrier to secure the seal. The carrier has an axially outwardly facing annular pocket accommodating a foam dust excluder into which a flange of a wear sleeve extends to protect the PTFE seal from debris. Additionally, the seal has a clamping ring having an axially extending first leg providing a second mating surface radially inwardly and generally parallel to the first mating surface of the outer member.Type: GrantFiled: October 22, 2002Date of Patent: March 9, 2004Assignee: Federal-Mogul World Wide, Inc.Inventors: John Christopher Kapcoe, Benjamin Cutler Clark
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Patent number: 6434649Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: October 14, 1998Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Equator TechnologiesInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath
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Patent number: 6347344Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.Type: GrantFiled: October 14, 1998Date of Patent: February 12, 2002Assignees: Hitachi, Ltd., Equator Technologies, Inc.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar