Abstract: Polarimetric transceiver front-ends and polarimetric phased array transceivers include two receive paths configured to receive signals from an antenna, each including a respective variable phase shifter. A first transmit path is connected to the variable phase shifter of one of the two receive paths and is configured to send signals to the antenna. A transmit/receive switch is configured to select between the first transmit path and the two receive paths for signals. The transmit/receive switch has an element that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: Polarimetric transceiver front-ends and polarimetric phased array transceivers include two receive paths configured to receive signals from an antenna, each including a respective variable phase shifter. A first transmit path is connected to the variable phase shifter of one of the two receive paths and is configured to send signals to the antenna. A transmit/receive switch is configured to select between the first transmit path and the two receive paths for signals. The transmit/receive switch has an element that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: an An arm for a material handling machine includes a first plate, a second plate, and a pair of side walls. The second plate includes two opposite edges and a first of the pair of side walls is welded inward of the first edge of the second plate. A second of the pair of side walls is welded inward of the opposite edge of the second pate to form two flanges, with each of the two flanges extending on opposite sides of the second plate and having at least one hole at each of its ends. Each of the flanges has a length that is longitudinal with respect to the arm and a width that is transverse with respect to the arm and the length of each flange is between ? and ? of the length of the arm.

Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

Abstract: A method of mounting an attachment on an arm of a material handling machine including the steps of: (a) providing an arm including a first plate, a second plate and a pair of side walls welded to each of the first plate and the second plate, the arm having a connector for pivotable mounting of the attachment at a first end of the arm and a connector for pivotable mounting to a further component of the material handling machine at a second end of the arm opposite to the first end; wherein the second plate has two opposite edges and a first of the pair of side walls is welded inward of one edge and a second of the pair of side walls is welded inward of the other edge to form two flanges, each of the two flanges extending on opposite sides of the second plate and each of the two flanges having at least one hole at each of its ends; (b) providing a bracket including a mounting plate having a pair of lugs for supporting an actuator for the attachment; the pair of lugs being positioned in a central portion of th

Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

Abstract: First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Abstract: A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state.

Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point.

Abstract: Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.

Abstract: A format converter in which the data input is a 16 bit wide interface. The circuit finds the 66-bit coding block boundaries. In one embodiment, a circuit presents the 66-bit data blocks at the output in an aligned format. The circuit relies on control inputs from a state machine which controls the operating mode and to which it delivers status information. The two main operating modes are the “normal data” mode or the “hunt” mode for the 66-bit block boundaries.

Abstract: Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.