Abstract: An implantable cardiac defibrillator is provided having an energy source, a capacitor, and means coupled to the energy source for charging the capacitor. The capacitor comprises a planar layered structure of anode plates, cathode plates and means separating the anode plates and cathode plates. A polymeric envelope containing electrolyte encloses the layered structure. Electrical contact means extend from the anodes and cathodes to outside the envelope.

Abstract: An implantable medical device includes electrodes coupled to a patient's heart and sensing circuitry having inputs connected to the electrodes for sensing analog cardiac electrical signals from one of the atrial or ventricular channels. The sensing circuitry includes waveform digitization network means for converting the analog atrial or ventricular electrical signals into a parallel output format sign/magnitude digitized output signal.

Abstract: An implantable cardiac defibrillator employing a switched capacitor filter stage having charge steering resistors connected in series with corresponding switched capacitors that are coupled to a sensitive node of an operational amplifier. The stored channel charges in associated switches when they are tuned off are directed away from the sensitive node. The switches associated with the switched capacitors are operated by control signals having a generally trapezoidal shaped waveform so as to slowly turn off the same, thereby reducing clock feedthrough and charge injection induced offset voltage on the output of the operational amplifier.

Abstract: An implantable medical device includes electrodes coupled to a patient's heart and sensing circuitry having inputs connected to the electrodes for sensing cardiac electrical signals. The sensing circuitry includes a digital waveform analyzer system which performs direct analysis of digitized ECG heart signals from the atrial and/or ventricular channels. This eliminates the need for the system microprocessor to perform direct analysis on raw ECG data. The benefit being that complex software algorithms are not required, saving microprocessor memory space. System current drain is also reduced since the microprocessor need not be active during every ECG sample.

Abstract: An implantable cardiac defibrillator employing a switched capacitor filter stage having charge steering resistors connected in series with corresponding switched capacitors that are coupled to a sensitive node of an operational amplifier. The stored channel charges in associated switches when they are turned off are directed away from the sensitive node. The switches associated with the switched capacitors are operated by control signals having a generally trapezoidal shaped waveform so as to slowly turn off the same, thereby reducing clock feedthrough and charge injection induced offset voltage on the output of the operational amplifier.

Abstract: An implantable cardiac defibrillator includes electrodes coupled to a patient's heart, a sensing system having inputs connected to the electrodes for sensing cardiac electrical signals from the atrial and/or ventricular channels, means for storing a charge, and means for delivering a shock to the heart. The sensing system includes switched capacitor means for amplifying the cardiac electrical signal with non-binary gain changing steps.

Abstract: An implantable cardiac defibrillator includes electrodes coupled to a patient's heart, sensing circuitry having inputs connected to the electrodes for sensing cardiac electrical signals, charging means for storing a charge, and discharge means for delivering a shock to the heart. The sensing circuitry includes switched capacitor gain/filter means for providing an output signal which is transient-free during a gain change operation and which maintains a constant filter bandwidth for each gain setting.

Abstract: An implantable cardiac defibrillator employing a switched capacitor stage wherein the switches are clocked in a non-50%/50% ratio such that an operational amplifier has greater than 50% of the clock period to acquire the desired voltage and less than 50% of the clock period to hold the acquired voltage, thereby allowing the circuit to run at an overall lower current drain.

Abstract: A heart pacemaker detects pace-terminable tachycardia conditions in the atrium of the heart in accordance with selected high rate, rate stability, sudden onset and sustained high rate criteria. When a pace-terminable tachycardia is detected, programmed treatment modalities are applied to attempt to terminate the tachycardia. The tachycardia is treated by applying timed bursts of electrical pulses in formats defined by programmed primary and secondary treatment modalities. The primary and secondary treatments may be applied in an order which is dependent upon the prior successful treatment of similar tachycardias. The pacemaker may also utilize remembered treatment values which were successfully applied to treat similar tachycardias. The pacemaker may be programmed to restart the primary and secondary modes of treatment in the event that the modes initially failed to terminate a tachycardia. The pacemaker may also be programmed to limit the rate of burst pulses to avoid overstimulating the heart.

Abstract: A heart pacemaker detects pace-terminable tachycardia conditions in the atrium of the heart in accordance with selected high rate, rate stability, sudden onset and sustained high rate criteria. When a pace-terminable tachycardia is detected, programmed treatment modalities are applied to attempt to terminate the tachycardia. The tachycardia is treated by applying timed bursts of electrical pulses in formats defined by programmed primary and secondary treatment modalities. The primary and secondary treatments may be applied in an order which is dependent upon the prior successful treatment of similar tachycardias. The pacemaker may also utilize remembered treatment values which were successfully applied to treat similar tachycardias. The pacemaker may be programmed to restart the primary and secondary modes of treatment in the event that the modes initially failed to terminate a tachycardia. The pacemaker may also be programmed to limit the rate of burst pulses to avoid overstimulating the heart.

Abstract: A cardiac pacemaker lead has a structure which provides an enhanced sensitivity to atrial P-waves. The distal end of the lead has two sensing electrodes disposed thereon to contact atrial cardiac tissue and to detect near field P-waves with greater sensitivity than far field R-waves.

Abstract: A priority switching circuit for providing a minimum voltage to a voltage sensitive load while charging a second load drawing a high current includes a battery, comparator, capacitor, and a voltage regulator. The output of the comparator causes the battery to be connected to the capacitor whenever the voltage across the capacitor drops below a predetermined minimum and causes the battery to be connected to the high current load when the voltage across the capacitor rises to a predetermined maximum. The circuit provides a varied switching frequency as the internal impedance of the battery increases with age. The voltage regulator provides a constant reference voltage which is used by the comparator to provide the switching control signals.