Patents by Inventor Benjamin David Briggs

Benjamin David Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180366408
    Abstract: A method of forming a semiconductor device includes forming a porous dielectric layer including a recessed portion, forming a conductive layer in the recessed portion of the porous dielectric layer, and forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 20, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlef H. DEPROSPO, Huai HUANG, Christopher J. PENNY, Michael RIZZOLO
  • Publication number: 20180354291
    Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium an anti-counterfeiting system, include a production circuit configured to produce a Directed Self-Assembly (DSA) pattern including a unique pattern, an analysis circuit configured to analyze the unique pattern, an embedding circuit configured to embed the unique pattern on a document, and a verification circuit configured to verify that the unique pattern embedded on the document corresponds to the document.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Patent number: 10150323
    Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium, include a production circuit configured to produce a Directed Self-Assembly (DSA) pattern including a unique pattern, an analysis circuit configured to analyze the unique pattern, an embedding circuit configured to embed the unique pattern on a document, and a verification circuit configured to verify that the unique pattern embedded on the document corresponds to the document.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Patent number: 10134674
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Patent number: 10109579
    Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180249271
    Abstract: A binaural audio calibration method, system, and computer program product for using behavioral data and sensor data to calibrate binaural audio to a specific user and creating a personalized binaural audio which can lead to greater immersion and allow user attention to be more effectively controlled.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Leigh Anne Hodges Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Gunars Sipolins
  • Publication number: 20180190585
    Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlet H. DEPROSPO, Huai HUANG, Christopher J. PENNY, Michael RIZZOLO
  • Patent number: 9997451
    Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180122692
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Publication number: 20180122691
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Publication number: 20180114723
    Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 26, 2018
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Patent number: 9953865
    Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Publication number: 20180005937
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo, Nicole Adelle Saulnier
  • Publication number: 20180005941
    Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlet H. DEPROSPO, Huai HUANG, Christopher J. PENNY, Michael RIZZOLO
  • Publication number: 20180005883
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlet H. DEPROSPO, Michael RIZZOLO
  • Publication number: 20170344722
    Abstract: A cognitive health management method, system, and non-transitory computer readable medium, include analyzing user input data of a first user by comparing the user input data of the first user to medical data in the database, and providing both of: a recommendation to the first user based on the comparison of the user input data of the first user to the medical data of the database, and a result feedback including a conclusion of the analyzing to a result feedback section of the database.
    Type: Application
    Filed: May 27, 2016
    Publication date: November 30, 2017
    Inventors: Maryam Ashoori, Benjamin David Briggs, Lawrence A. Clevenger, Leigh Anne Hodges Clevenger, Jonathan Hudson Connell, II, Michael Rizzolo
  • Patent number: 9780035
    Abstract: A method for fabricating a metallization layer of a semiconductor device, in which copper is used for an interconnect material and cobalt is used to encapsulate the copper, includes introducing a material that will form an alloy with cobalt and resist a degradation of an effect of the cobalt on encapsulating the copper.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Publication number: 20170249506
    Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium an anti-counterfeiting system, include a production circuit configured to produce a Directed Self-Assembly (DSA) pattern including a unique pattern, an analysis circuit configured to analyze the unique pattern, an embedding circuit configured to embed the unique pattern on a document, and a verification circuit configured to verify that the unique pattern embedded on the document corresponds to the document.
    Type: Application
    Filed: February 29, 2016
    Publication date: August 31, 2017
    Inventors: Benjamin David Briggs, Lawrence A. Clevengen, Bartlet H. DeProspo, Michael Rizzolo