Patents by Inventor Benjamin Dumont

Benjamin Dumont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180090389
    Abstract: An integrated circuit includes FDSOI-type MOS transistors formed inside and on top of a semiconductor layer resting on an insulating layer. The transistors include a logic MOS transistor of a first conductivity type, a logic MOS transistor of a second conductivity type, and an analog MOS transistor of the first conductivity type, A gate stack of the logic transistors successively includes a gate insulator layer, a first titanium nitride layer, a lanthanum layer, and a second titanium nitride layer. A gate stack of the analog transistor includes the gate insulator layer, the lanthanum layer and the second titanium nitride layer but not the first titanium nitride layer.
    Type: Application
    Filed: March 14, 2017
    Publication date: March 29, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Guillaume C. Ribes, Benjamin Dumont, Franck Arnaud
  • Patent number: 7960255
    Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: June 14, 2011
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V.
    Inventors: Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Markus Müller
  • Publication number: 20100203712
    Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.
    Type: Application
    Filed: September 22, 2008
    Publication date: August 12, 2010
    Inventors: Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Markus Müller