Patents by Inventor Benjamin DUONG
Benjamin DUONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12677682Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.Type: GrantFiled: July 1, 2022Date of Patent: July 7, 2026Assignee: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Robert A. May, Brandon Marin, Benjamin Duong, Suddhasattwa Nad, Hsin-Wei Wang, Leonel Arana, Darko Grujicic
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Patent number: 12660662Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.Type: GrantFiled: June 30, 2022Date of Patent: June 16, 2026Assignee: Intel CorporationInventors: Kristof Darmawikarta, Srinivas Pietambaram, Benjamin Duong, Haobo Chen
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Patent number: 12628669Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass layers within a package that include one or more high aspect ratio TGV that are filled with conductive material. The TGV extends from a first side of the glass layer to a second side of the glass layer opposite the first side and are filled with conductive material to provide a high-quality electrical connection between the first side of the glass layer and the second side of the glass layer, where a portion of the wall of the TGV includes titanium. Other embodiments may be described and/or claimed.Type: GrantFiled: September 21, 2021Date of Patent: May 12, 2026Assignee: Intel CorporationInventors: Darko Grujicic, Sashi S. Kandanur, Helme A. Castro De La Torre, Srinivas V. Pietambaram, Marcel Wall, Suddhasattwa Nad, Rengarajan Shanmugam, Benjamin Duong
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Publication number: 20260090427Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, and a second substrate over the first substrate, where the second substrate comprises an organic buildup layer. In an embodiment, a first width of the first substrate is greater than a second width of the second substrate. In an embodiment, an edge between a first corner of the first substrate and a second corner of the first substrate comprises a curve.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Bohan SHAN, Wei LI, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Ziyin LIN, Dingying David XU, Hongxia FENG, Yiqun BAI, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Benjamin DUONG, Gang DUAN, Srinivas Venkata Ramanuja PIETAMBARAM, Rui ZHANG, Mohit GUPTA
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Publication number: 20260090430Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Bohan SHAN, Wei LI, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Haobo CHEN, Dingying David XU, Hongxia FENG, Yiqun BAI, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Benjamin DUONG, Gang DUAN, Ziyin LIN, Srinivas Venkata Ramanuja PIETAMBARAM
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Publication number: 20260090433Abstract: 3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Applicant: Intel CorporationInventors: Zhixin Xie, Mohamed Saber, Bohan Shan, Anastasia Arrington, Clay Arrington, Jigneshkumar Patel, Catherine Mau, Ryan Carrazzone, Haobo Chen, Wei Li, Kyle Arrington, Ziyin Lin, Dingying Xu, Hongxia Feng, Hiroki Tanaka, Brandon Marin, Jeremy Ecton, Benjamin Duong, Gang Duan, Srinivas Pietambaram, Praveen Sreeramagiri, Andrew Jimenez, Yekan Wang, Jung Kyu Han
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Publication number: 20260090429Abstract: Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Bohan SHAN, Wei LI, Ryan CARRAZZONE, Jose WAIMIN, Kyle ARRINGTON, Haobo CHEN, Dingying David XU, Hongxia FENG, Yiqun BAI, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Benjamin DUONG, Gang DUAN, Srinivas Venkata Ramanuja PIETAMBARAM, Clay ARRINGTON
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Publication number: 20260090431Abstract: Integrated circuit (IC) devices having glass layers in package substrates. An IC device substrate may include a solid glass layer and a polymer layer that forms a frame on sidewalls and an upper surface of the glass layer, and the glass layer may include a tab or nubbin that extends through the frame of the polymer layer. The substrate may include electrical vias through the substrate and electrical traces on one or both sides of the substrate. Portions of a glass panel (for example, along saw streets) may be removed and replaced with polymer frame materials. The glass panel may be sawn into glass substrates by sawing through the polymer and through glass bridge portions, which may be of minimal thickness.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Applicant: Intel CorporationInventors: Hiroki Tanaka, Robert May, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Bohan Shan, Haobo Chen, Bai Nie, Whitney Bryks, Benjamin Duong, Brandon C. Marin
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Publication number: 20260077433Abstract: According to the various aspects, a present tool assembly or apparatus includes a water delivery component configured to direct water to a workpiece, and a cutting component for removing material to form cut-streets for die singulation. The present tool assembly is configured to operate to remove build-up layers and other layers from a glass core of the workpiece in a wet environment and a dry environment, at cut-street locations, and perform methods for dicing the workpiece.Type: ApplicationFiled: September 13, 2024Publication date: March 19, 2026Inventors: Praveen SREERAMAGIRI, Robin McREE, Jesse JONES, Gang DUAN, Yi LI, Ibrahim EL KHATIB, Srinivas PIETAMBARAM, Kari HERNANDEZ, Soham AGARWAL, Benjamin DUONG, Pratyush MISHRA, Pratyasha MOHAPATRA
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Patent number: 12573536Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.Type: GrantFiled: June 10, 2024Date of Patent: March 10, 2026Assignee: Intel CorporationInventors: Benjamin Duong, Michael Garelick, Darko Grujicic, Tarek Ibrahim, Brandon C. Marin, Sai Vadlamani, Marcel Wall
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Patent number: 12575427Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first sidewall and a second portion that includes a second sidewall, wherein the first sidewall includes seed metallization and the second sidewall excludes the seed metallization.Type: GrantFiled: September 14, 2021Date of Patent: March 10, 2026Assignee: Intel CorporationInventors: Jeremy D Ecton, Darko Grujicic, Suddhasattwa Nad, Benjamin Duong
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Patent number: 12568817Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate, and a second layer is over the trace, where the second layer comprises silicon and nitrogen. In an embodiment, the second layer is chemically bonded to the one of the first layers.Type: GrantFiled: March 29, 2022Date of Patent: March 3, 2026Assignee: Intel CorporationInventors: Yi Yang, Rahul N. Manepalli, Suddhasattwa Nad, Marcel Wall, Benjamin Duong
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Patent number: 12560771Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a photonic integrated circuit and an in situ formed waveguide. In selected examples, the electronic device includes a photonic integrated circuit coupled to an electronic integrated circuit, in a glass layer, where a waveguide is formed in the glass layer.Type: GrantFiled: September 21, 2021Date of Patent: February 24, 2026Assignee: Intel CorporationInventors: Bai Nie, Pooya Tadayon, Leonel R. Arana, Yonggang Li, Changhua Liu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Hari Mahalingam, Benjamin Duong
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Publication number: 20260011704Abstract: Embodiments disclosed herein include optical communication modules and optoelectronic packages. In an embodiment, an optical communication module comprises a substrate, a transistor over the substrate, an array of micro light emitting diodes (LEDs) over the transistor, and a connector over the array of micro LEDs.Type: ApplicationFiled: August 4, 2022Publication date: January 8, 2026Inventors: Benjamin DUONG, Vinod ADIVARAHAN, Liqiang CUI, Brandon C. MARIN, Sandeep GAAN
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Publication number: 20260005079Abstract: Thin glass cores for integrated circuit (IC) packages. Recesses in a glass core may be selectively etched into a frontside and/or backside of the glass core to locally reduce the thickness of glass. A dielectric material may be applied over the glass to backfill the recesses. The glass may then be further thinned from a same side as the recess to reduce the thickness of regions outside of the recesses. Alternatively, the glass may then be further thinned from a side of the glass opposite the recess to reduce the thickness of regions outside of the recesses and also remove the lesser thickness of glass remaining at the location of the recess. Panels comprising the thin glass core may then be built-up with routing metallization and assembled with IC die.Type: ApplicationFiled: June 28, 2024Publication date: January 1, 2026Applicant: Intel CorporationInventors: Jeremy Ecton, Kristof Darmawikarta, Brandon Marin, Gang Duan, Srinivas Pietambaram, Benjamin Duong, Soham Agarwal, Kari Hernandez, Pratyush Mishra, Pratyasha Mohapatra, Bohan Shan, Hiroki Tanaka
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Publication number: 20260001297Abstract: Embodiments disclosed herein include an apparatus that comprises a substrate. In an embodiment, the substrate comprises a glass layer. In an embodiment, a frame is provided around a perimeter of the substrate. In an embodiment, the frame is over a top surface, a bottom surface, and a sidewall surface of the substrate. In an embodiment, the frame comprises a conductive material.Type: ApplicationFiled: June 26, 2024Publication date: January 1, 2026Inventors: Hiroki TANAKA, Robert Alan MAY, Whitney BRYKS, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Jesse JONES, Bohan SHAN, Bai NIE, Benjamin DUONG, Haobo CHEN, Brandon C. MARIN
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Publication number: 20260005078Abstract: An apparatus comprises a glass core comprising a top surface and a bottom surface opposite the top surface. A plurality of vias extending between the top and bottom surfaces. A metallization layer is over at least a portion of the top surface. An edge is between the top and bottom surfaces. The edge comprises one or more protrusions or one or more cavities. Each of the protrusions or cavities comprises a first surface parallel to the top surface, a second surface non-parallel to the top surface, and a polymer or a metal on the first or second surface.Type: ApplicationFiled: June 27, 2024Publication date: January 1, 2026Applicant: Intel CorporationInventors: Soham Agarwal, Whitney Bryks, Aaditya Anand Candadai, Yi Cao, Kristof Darmawikarta, Gang Duan, Benjamin Duong, Jeremy Ecton, Mahdi Mohammadighaleni, Kari Hernandez, Andrew Jimenez, Houssam Jomaa, Manohar Konchady, Xinyu Li, Minglu Liu, Brandon Marin, Pratyush Mishra, Pratyasha Mohapatra, Seyyed Yahya Mousavi, Travis Palmer, Joseph Peoples, Srinivas Pietambaram, Bohan Shan, Joshua Stacey, Hiroki Tanaka, Yekan Wang, Hong Seung Yeon, Yingying Zhang
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Publication number: 20260005160Abstract: Embodiments disclosed herein include an apparatus that includes a substrate that comprises a glass layer. In an embodiment, a frame is provided around the substrate, and a gap is provided between an edge of the substrate and an interior edge of the frame. In an embodiment, a fill layer is provided in the gap, and the fill layer comprises a dielectric material. In an embodiment, a ring is provided over the fill layer around a perimeter of the substrate. In an embodiment, the ring comprises a metallic material.Type: ApplicationFiled: June 28, 2024Publication date: January 1, 2026Inventors: Manohar KONCHADY, Andrew JIMENEZ, Son NGUYEN, Hiroki TANAKA, Yekan WANG, Srinivas Venkata Ramanuja PIETAMBARAM, Robert Alan MAY, Jacob VEHONSKY, Whitney BRYKS, Bohan SHAN, Gang DUAN, Bai NIE, Xiyu HU, Benjamin DUONG, Haobo CHEN, Brandon C. MARIN, Zhixin XIE, David VICKERY, Nirupama CHAKRAPANI, Dilan SENEVIRATNE, Jung Kyu HAN, Thomas HEATON
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Patent number: 12504581Abstract: Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.Type: GrantFiled: September 15, 2021Date of Patent: December 23, 2025Assignee: Intel CorporationInventors: Kristof Darmawikarta, Benjamin Duong, Srinivas V. Pietambaram, Tarek A. Ibrahim, Hari Mahalingam, Bai Nie
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Patent number: 12449600Abstract: Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.Type: GrantFiled: September 23, 2021Date of Patent: October 21, 2025Assignee: Intel CorporationInventors: Jeremy Ecton, Leonel Arana, Whitney Bryks, Haobo Chen, Benjamin Duong, Changhua Liu, Brandon Marin, Srinivas Pietambaram