Patents by Inventor Benjamin DUONG
Benjamin DUONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112100Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Robert May, Hiroki Tanaka, Tarek Ibrahim, Lilia May, Jason Gamba, Benjamin Duong, Brandon Marin, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Jeremy Ecton
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Publication number: 20250110720Abstract: System and computer-implemented method for updating applications running in a distributed computing system uses an update agent associated with an existing application to make a request for update information regarding the existing application to a service to receive a response that includes a target version of the existing application and an update window of time, which is based on information contained in the request for update information. A deployment of the target version of the existing application within the update window of time is coordinated by the update agent when the target version is newer than a current version of the existing application.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: David Mark William Byard, Praagyan Pokharel, Benjamin Duong, Ron Passerini
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Publication number: 20250112124Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Leonel Arana, Gang Duan, Benjamin Duong, Hongxia Feng, Tarek Ibrahim, Brandon C. Marin, Tchefor Ndukum, Bai Nie, Srinivas Pietambaram, Bohan Shan, Matthew Tingey
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Publication number: 20250085433Abstract: Disclosed are methods, apparatuses, and systems. A method can include receiving, by one or more processors, navigation data from a navigation system. The method can include receiving first correction data from a first correction source and receiving second correction data from a second correction source. The method can include determining first positional data based on the navigation data and the first correction data and second positional data based on the navigation data and the second correction data. The method can include determining a first accuracy value associated with the first positional data and a second accuracy value associated with the second positional data. The method can include selecting one of the first navigation system and the second navigation system for positional tracking based, in part, on at least one of the first accuracy value and the second accuracy value.Type: ApplicationFiled: September 11, 2024Publication date: March 13, 2025Applicant: Hemisphere GNSS, Inc.Inventors: Jian Ping Chen, Benjamin Brownlee, Viet Duong, Alim Kanji, Michael Whitehead
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Publication number: 20250014954Abstract: Hybrid cores including adhesive promotion layers and related methods are disclosed. An example substrate core for an integrated circuit disclosed herein includes a frame including interior edge, a glass panel including an exterior edge, and an adhesion promotion layer disposed between the interior edge and the exterior edge.Type: ApplicationFiled: June 27, 2024Publication date: January 9, 2025Inventors: Soham Agarwal, Gang Duan, Benjamin Duong, Darko Grujicic, Kari Hernandez, Lei Jin, Jesse Cole Jones, Zheng Kang, Shayan Kaviani, Yi Li, Sandrine Lteif, Pratyush Mishra, Mahdi Mohammadighaleni, Pratyasha Mohapatra, Logan Myers, Suresh Tanaji Narute, Srinivas Venkata Ramanuja Pietambaram, Umesh Prasad, Rengarajan Shanmugam, Elham Tavakoli, Marcel Arlan Wall, Yekan Wang, Ehsan Zamani
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Publication number: 20250006671Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Inventors: Marcel Arlan Wall, Hamid Azimi, Rahul N. Manepalli, Srinivas Venkata Ramanuja Pietambaram, Darko Grujicic, Steve Cho, Thomas L. Sounart, Gang Duan, Jung Kyu Han, Suddhasattwa Nad, Benjamin Duong, Shayan Kaviani
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Publication number: 20250006781Abstract: Carbon nanofiber capacitor apparatus and related methods are disclosed herein. An example apparatus includes an integrated circuit package substrate, and a capacitor provided in the integrated circuit package substrate. The capacitor includes a carbon fiber array, a dielectric film positioned on the carbon fiber array, and an electrode film positioned on the dielectric film.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Inventors: Thomas Sounart, Henning Braunisch, Aleksandar Aleksov, Kristof Darmawikarta, Darko Grujicic, Marcel Wall, Suddhasattwa Nad, Benjamin Duong, Shayan Kaviani
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Patent number: 12165994Abstract: An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate, a plurality of integrated circuit devices electrically attached to the package substrate, wherein each integrated circuit device of the plurality of integrated circuit devices includes an active surface and a backside surface, and wherein a first integrated circuit device and a second integrated circuit device of the plurality of integrated circuit devices includes radio frequency logic circuitry and a radio frequency antenna formed in or attached thereto, and a radio frequency waveguide on the backside surface of the first integrated circuit device and on the backside surface of the second integrated circuit device.Type: GrantFiled: September 17, 2020Date of Patent: December 10, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Kristof Darmawikarta, Benjamin Duong, Telesphor Kamgaing, Miranda Ngan, Srinivas Pietambaram
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Patent number: 12159844Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.Type: GrantFiled: September 23, 2020Date of Patent: December 3, 2024Assignee: Intel CorporationInventors: Benjamin Duong, Roy Dittler, Darko Grujicic, Chandrasekharan Nair, Rengarajan Shanmugam
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Publication number: 20240347402Abstract: Methods and apparatus to reduce delamination in hybrid cores are disclosed. An example hybrid core of an integrated circuit (IC) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon Christian Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Leonel Arana, Benjamin Duong
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Publication number: 20240345324Abstract: An integrated circuit package includes a substrate with an integrated circuit device mounting surface, and at least one optical fiber mount in the substrate. The optical fiber mount includes a support having at least one optical fiber mounting channel, and the optical fiber mounting channel is configured to mount at least one clad optical fiber.Type: ApplicationFiled: April 11, 2023Publication date: October 17, 2024Applicant: Intel CorporationInventors: Benjamin Duong, Kristof Darmawikarta, Soham Agarwal, Marcel Said, Sandeep Gaan
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Publication number: 20240327201Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Inventors: Numair Ahmed, Mohammad Mamunur Rahman, Suddhasattwa Nad, Sashi Kandanur, Darko Grujicic, Benjamin Duong, Srinivas Pietambaram, Tarek Ibrahim, Whitney Bryks
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Publication number: 20240332100Abstract: Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Inventors: Pratyush Mishra, Marcel Wall, Sashi Kandanur, Pooya Tadayon, Srinivas Pietambaram, Benjamin Duong, Suddhasattwa Nad
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Publication number: 20240331921Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Applicant: Intel CorporationInventors: Benjamin Duong, Michael Garelick, Darko Grujicic, Tarek Ibrahim, Brandon C. Marin, Sai Vadlamani, Marcel Wall
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Publication number: 20240312853Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 14, 2023Publication date: September 19, 2024Inventors: Sashi S. KANDANUR, Srinivas V. PIETAMBARAM, Darko GRUJICIC, Brandon C. MARIN, Suddhasattwa NAD, Benjamin DUONG, Gang DUAN, Mohammad Mamunur RAHMAN, Numair AHMED
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Publication number: 20240312888Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 14, 2023Publication date: September 19, 2024Inventors: Sashi S. KANDANUR, Srinivas V. PIETAMBARAM, Darko GRUJICIC, Brandon C. MARIN, Suddhasattwa NAD, Benjamin DUONG, Gang DUAN, Mohammad Mamunur RAHMAN, Numair AHMED
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Patent number: 12057252Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.Type: GrantFiled: September 23, 2020Date of Patent: August 6, 2024Assignee: Intel CorporationInventors: Benjamin Duong, Michael Garelick, Darko Grujicic, Tarek Ibrahim, Brandon C. Marin, Sai Vadlamani, Marcel Wall
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Publication number: 20240251017Abstract: System and computer-implemented method for connecting a proxy client to a transport client through a transport service with a plurality of stateless transport server nodes in a distributed computing system uses a command channel established from the transport client to a first transport server node in the transport service. A second transport server node in the transport service is selected for a connection request from the proxy client. The first transport server node is connected from the second transport server node when the second transport server node is not the first transport server node with the command channel so that connectivity between the proxy client and the transport client is established through the first transport server node and the second transport server node.Type: ApplicationFiled: January 25, 2023Publication date: July 25, 2024Inventors: David Mark William Byard, Benjamin Duong, Praagyan Pokharel
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Publication number: 20240231922Abstract: A method for removing redundant channels between a client and pods of a service is provided. Some embodiments include sending, from the client to the service, a first request for an application exposed by the service, the first request corresponding to a request for a first channel, receiving from a first pod associated with the service, a response indicating acceptance of the first request, establishment of the first channel between the first pod and the client, and an identifier of the first pod, and storing an association between the first channel and the name of the first pod. In some embodiments, the method includes determining whether any pod is associated with multiple channels in the data structure and in response to determining that the first pod is associated with the first channel and one or more other channels, shutting down the one or more other channels.Type: ApplicationFiled: January 11, 2023Publication date: July 11, 2024Inventors: Ryan BRADFORD, Benjamin DUONG
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Publication number: 20240219644Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Suddhasattwa Nad, Benjamin Duong, Hiroki Tanaka, Brandon Marin, Jeremy Ecton, Gang Duan, Srinivas Pietambaram, Hari Mahalingam