Abstract: Disclosed are systems and methods which provide phase shifting of signals while minimizing signal attenuation associated with providing such phase shifting. Preferred embodiments provide a compact polyphase filter structure in which the geometry of the polyphase filter both minimizes parasitic capacitance and signal transmission paths therein. A polyphase filter of a preferred embodiment utilizes a radial pinwheel structure providing a geometry in which successive circuit components are disposed very near one another and in an orientation to accommodate very short connections therebetween. Embodiments may include the use of a buffer at the outputs of the polyphase filter circuit to reduce the amount of parasitics associated with the polyphase filter.

Abstract: An analog-to-digital converter comprises a modulator connected to an analog input signal, a decimator connected to the output of the modulator, a normalizer connected to the output of the modulator and forming a digital output signal, and a programmable gain control circuit connected to the output of the normalizer and providing feedback gain control to the modulator and the decimator.

Abstract: In a double-sided pulse width modulator, an amplifier has a first input connected to a first reference potential, a second input, and an output. A first bank of storage elements have a first terminal connected to the second input of the amplifier, and a second terminal. A first bank of switches have an output terminal connected to a second terminal of the storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of the modulator and a polarity control bit for a first value to be input into the input terminals. A feedback storage element is connected in parallel with a first timing switch between the second input of the amplifier and the output of the amplifier. A comparator has a first input connected to a second reference potential, a second input, a timing enable input, and an output. A second bank of storage elements have a first terminal connected to the second input of the comparator, and a second terminal.

Abstract: The clock multiplying phase locked loop includes components for selectively setting a center frequency of a voltage controlled oscillator (VCO) to bias the VCO for operation within a selected range of input frequencies. To this end, the VCO is configured to output a signal at a selected center frequency based upon a tuning current provided to the VCO. Initially, a voltage input of the VCO is set to a reference voltage and a feedback signal is generated. The feedback signal, perhaps divided by N, is input to a phase-frequency detector. The phase-frequency detector also receives a reference frequency signal having a frequency at the selected center frequency. The detector outputs an UP or DOWN signal indicating whether the feedback signal is greater or less than the reference frequency signal.

Abstract: A VSLI transceiver chip incorporating an improved analog PLL circuit for recovering a digital clock signal from a digital data signal having pulse widths which may vary during each data cycle. The analog PLL clock recovery circuit comprises a phase detector, a gain control circuit, a variable current charge pump, a loop filter and a variable frequency oscillator. The phase detection means for detecting, during each data cycle, the phase error between the digital data signal and recovered digital clock signal, and produces first end second digital control pulse signals in response to the detection of the phase error. The gain control means produces third and fourth digital control pulse signals during each data cycle.