Abstract: A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Abstract: A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Abstract: A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC.

Abstract: A subtraction circuit. The novel subtraction circuit includes a first circuit for providing an impedance between an input node and an output node, a second circuit for generating a first current and applying the first current to the output node to produce a desired voltage drop between the input and output nodes, and a third circuit for independently generating a second current relative to the first current and applying the second current to the input node to regulate a current input to the first circuit at the input node. The second and third circuits are implemented using two digital to analog converters (DACs), a precision DAC for generating the first current and a non-trimmed “dummy” DAC for generating the second current. In an illustrative embodiment, the subtraction circuit is used in the reconstruction stage of a subranging analog to digital converter.

Abstract: A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC.

Abstract: An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signal's chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal.

Abstract: An RF transceiver with a low power chirp acquisition mode includes a pulse detection circuit, which initiates a low power chirp acquisition mode when an appropriate input pulse is received. While in chirp acquisition mode, all transceiver circuitry not required to determine the chirp rate is powered down, a low power fast-hopping LO generator is powered up to provide one or more LO signals to demodulate the incoming signal, and an active bandpass filter connected to filter the demodulated output is arranged to extend the width of its passband to include the chirp rate. The filtered signal is digitized with an ADC and processed to determine the incoming signal's chirp rate. The low power LO generator comprises a look-up table which provides a plurality of digital output word sequences, each of which represents a discrete LO frequency, to a sine-weighted DAC. The resulting varying frequency analog output signal is multiplied to produce the discrete LO signals needed to demodulate the input signal.

Abstract: A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution.

Abstract: A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.

Abstract: A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.

Abstract: A diode bridge includes a plurality of diodes for coupling an input voltage signal to a holding capacitor for sampling when the diodes are forward biased, and uncoupling the voltage signal from the capacitor for holding when the diodes are reverse biased. The diode bridge has first and second bias current nodes. A constant current drain causes a constant bias current to flow out of the bridge. A transistor connects the first node to the drain for forward biasing the diodes, whereas a transistor connects the second node to the drain for reverse biasing the diodes. A bootstrap amplifier (A2) produces a variable control voltage which controls a pair of voltage-controlled constant current sources to cause the constant bias current to flow therethrough into the bridge. A transistor (Q7) couples the control voltage to the first current source for forward biasing the diodes, whereas a transistor couples the control voltage to the second current source for reverse biasing the diodes.

Abstract: A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale.