Abstract: An apparatus includes a memory comprising executable instructions and a processor coupled to the memory and configured to execute the instructions. Executing the instructions causes the processor to receive a broadcast including measurement data captured by a first sensor, verify integrity of the measurement data, perform a quality control analysis on the measurement data by analyzing the measurement data using a quality control algorithm to form an analysis result, generate a response for broadcasting the analysis result, and broadcast the analysis result. The response comprises a determination of pass when the quality control analysis indicates that the measurement data passes the quality control analysis and a determination of fail, a suspected cause of the failure, and a recommended resolution for the suspected cause of the failure when the quality control analysis indicates that the measurement data fails the quality control analysis.

Abstract: A computer-implemented method comprising capturing measurement data via a first sensor suite, broadcasting the measurement data via short-range communication, receiving, via the short-range communication, a broadcast including a quality control analysis result corresponding to the measurement data and determined by a second sensor suite, acting on the quality control analysis result, and performing quality control analysis for a third sensor suite.

Abstract: A computer-implemented method comprising capturing measurement data via a first sensor suite, broadcasting the measurement data via short-range communication, receiving, via the short-range communication, a broadcast including a quality control analysis result corresponding to the measurement data and determined by a second sensor suite, acting on the quality control analysis result, and performing quality control analysis for a third sensor suite.

Abstract: An apparatus includes a memory comprising executable instructions and a processor coupled to the memory and configured to execute the instructions. Executing the instructions causes the processor to receive a broadcast including measurement data captured by a first sensor, verify integrity of the measurement data, perform a quality control analysis on the measurement data by analyzing the measurement data using a quality control algorithm to form an analysis result, generate a response for broadcasting the analysis result, and broadcast the analysis result. The response comprises a determination of pass when the quality control analysis indicates that the measurement data passes the quality control analysis and a determination of fail, a suspected cause of the failure, and a recommended resolution for the suspected cause of the failure when the quality control analysis indicates that the measurement data fails the quality control analysis.

Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

Abstract: A method of forming nickel monosilicide is provided that includes providing a silicon-containing surface, and ion implanting carbon into the silicon-containing surface. A nickel-containing layer is formed on the silicon-containing surface. Alloying the nickel-containing surface and the silicon-containing surface layer to provide a nickel monosilicide. The present disclosure also provides a non-agglomerated Ni monosilicide contact that includes a carbon interstitial dopant present in a concentration ranging from 1×1019 atoms/cm3 to 1×1021 atoms/cm3.

Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.