Patents by Inventor Benjamin G. Hess

Benjamin G. Hess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low density parity check circuit
    Patent number: 9411684
    Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 9, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Joe F. Holt, Suresh Rajgopal, Jacob B. Derouen, Benjamin G. Hess
  • LOW DENSITY PARITY CHECK CIRCUIT
    Publication number: 20150270851
    Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 24, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Joe F. Holt, Suresh Rajgopal, Jacob B. Derouen, Benjamin G. Hess