Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

Abstract: A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.

Abstract: A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

Abstract: A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.

Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.

Abstract: Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract: A logic design system operable to configure an integrated circuit device using custom logic design data is disclosed. The disclosed logic design system includes a computer-aided design tool that may be used to determine a memory space estimate based on a custom logic design data analysis. A memory size analysis may be performed on the custom logic design data to determine the maximum amount of stack memory that is required to execute procedures in the device. The logic design system may also monitor for changing memory requirements of the custom logic design. The logic design system may configure the device with the custom logic design data based on the memory space estimate.