Abstract: Embodiments described herein are generally directed to detecting security issues in a hardware design using IFT. In an example, dataflows are tracked within a hardware design represented in an HDL without instrumenting the HDL. Dataflow primitives are received specifying taint sources from which the dataflows are to be tracked. A baseline simulation trace log is obtained for a baseline RTL simulation of the hardware design by causing a simulator to perform the baseline RTL simulation during which none of the taint sources are altered. Injection simulation trace logs are obtained for injection RTL simulations by causing the simulator to perform an injection RTL simulation, for each taint source, during which the taint source is altered. The dataflows are then identified based on comparisons between the baseline and the injection simulation trace logs. A potential security issue is detected within the hardware design by applying a policy to the dataflows.

Abstract: Embodiments described herein are generally directed to detecting security issues in a hardware design using IFT. In an example, dataflows are tracked within a hardware design represented in an HDL without instrumenting the HDL. Dataflow primitives are received specifying taint sources from which the dataflows are to be tracked. A baseline simulation trace log is obtained for a baseline RTL simulation of the hardware design by causing a simulator to perform the baseline RTL simulation during which none of the taint sources are altered. Injection simulation trace logs are obtained for injection RTL simulations by causing the simulator to perform an injection RTL simulation, for each taint source, during which the taint source is altered. The dataflows are then identified based on comparisons between the baseline and the injection simulation trace logs. A potential security issue is detected within the hardware design by applying a policy to the dataflows.

Abstract: In one embodiment, a processor comprises a plurality of cores and a controller. Each of the plurality of cores may include: an execution circuit, a power measurement circuit to measure power consumption of the core and a first register to store a power-related context identifier to identify a process to be executed on the core. The controller may include: a plurality of energy status registers each associated with a power-related context identifier and to store energy consumption information of a process; and a control circuit coupled to the plurality of energy status registers, where the control circuit is to enable each of a plurality of processes to independently monitor the energy consumption information of the process and prevent each of the plurality of processes from monitoring the energy consumption information of other ones of the plurality of processes. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor comprises a plurality of cores and a controller. Each of the plurality of cores may include: an execution circuit, a power measurement circuit to measure power consumption of the core and a first register to store a power-related context identifier to identify a process to be executed on the core. The controller may include: a plurality of energy status registers each associated with a power-related context identifier and to store energy consumption information of a process; and a control circuit coupled to the plurality of energy status registers, where the control circuit is to enable each of a plurality of processes to independently monitor the energy consumption information of the process and prevent each of the plurality of processes from monitoring the energy consumption information of other ones of the plurality of processes. Other embodiments are described and claimed.