Patents by Inventor Benjamin H. Clark
Benjamin H. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7320086Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.Type: GrantFiled: December 1, 2005Date of Patent: January 15, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Tim Majni, Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark, Patrick L. Ferguson, Siamak Tavallaei, Jeffrey S. Autor, Christian H. Post, Dan Fink, Jeffery Galloway, Bret D. Roscoe
-
Patent number: 7194577Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.Type: GrantFiled: August 29, 2003Date of Patent: March 20, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren
-
Patent number: 7028213Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.Type: GrantFiled: September 28, 2001Date of Patent: April 11, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Tim Majni, Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark, Patrick L. Ferguson, Siamak Tavallaei, Jeffrey S. Autor, Christian H. Post, Dan Fink, Jeffery Galloway, Bret D. Roscoe
-
Patent number: 7010652Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.Type: GrantFiled: August 27, 2004Date of Patent: March 7, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark
-
Patent number: 6938133Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.Type: GrantFiled: September 28, 2001Date of Patent: August 30, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren
-
Patent number: 6832286Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.Type: GrantFiled: June 25, 2002Date of Patent: December 14, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren
-
Patent number: 6785785Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.Type: GrantFiled: January 25, 2001Date of Patent: August 31, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark
-
Publication number: 20040073767Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.Type: ApplicationFiled: August 29, 2003Publication date: April 15, 2004Inventors: Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren
-
Publication number: 20030236959Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.Type: ApplicationFiled: June 25, 2002Publication date: December 25, 2003Inventors: Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren
-
Publication number: 20030088805Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.Type: ApplicationFiled: September 28, 2001Publication date: May 8, 2003Inventors: Tim Majni, Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark, Patrick L. Ferguson, Siamak Tavallaei, Jeffrey S. Autor, Christian H. Post, Dan Zink, Jeffery Galloway, Bret D. Roscoe
-
Publication number: 20030070055Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.Type: ApplicationFiled: September 28, 2001Publication date: April 10, 2003Inventors: Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren
-
Publication number: 20020053010Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.Type: ApplicationFiled: January 25, 2001Publication date: May 2, 2002Inventors: Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark