Abstract: An integrated circuit includes a gain control terminal that provides for a choice of discrete gain values for circuitry on the IC. Typically, the gain control terminal is connected to a high voltage source (V.sub.DD), or a low voltage source (V.sub.SS), or optionally left unconnected. In addition, the integrated circuit provides a gain set terminal for connection to an external impedance, typically a resistor, and also includes gain set circuitry for determining the value of the resistor as falling within one range out of several possible ranges. Based upon the range thus determined, the gain set circuitry selects the discrete gain values that are available for choice by the gain control terminal. In this manner, a large range of gain values are available for use even though only a few need to be selected in actual operation of the IC. This technique minimizes external package terminals for the IC, and allows for gain setting by low tolerance resistors.

Abstract: CODECs and various other types of communication devices require timing information to enable them to transmit and receive digital information at the proper time. In the case of multiple CODECs on a single integrated circuit, this has typically required devoting terminals to provide separate transmit and receive frame synchronization pulses for each CODEC. Alternatively, a microprocessor interface may be included so that internal registers can be loaded with transmit and receive timing information. However, that approach limits timing flexibility. In the present invention, a "frame synchronization separation pulse" (FSEP) provides the separation in time between transmit and receive synchronization pulses. In this manner, the number of integrated circuit terminals required for synchronization may be reduced.