Patents by Inventor Benjamin Hayden

Benjamin Hayden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12541628
    Abstract: The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 3, 2026
    Assignee: Battelle Memorial Institute
    Inventors: Timothy A. McDonley, Andrew Elliott, Adam Kimura, Katie T. Liszewski, Thomas Kent, Josh Delozier, Benjamin Hayden
  • Publication number: 20250342303
    Abstract: In an approach to generating a DRC clean design, a method includes generating successive images of an integrated circuit, each of the successive images being associated with a different one of a plurality of layers of the integrated circuit; determining a layout of the integrated circuit in response to the successive images; collecting at least one measurement of at least one feature in the layout; and modifying the layout in response to the at least one measurement.
    Type: Application
    Filed: April 22, 2025
    Publication date: November 6, 2025
    Inventors: Andrew MCDONALD, Benjamin HAYDEN, Ryan MATTEI, Andrew SCHUELER, Adam Gakuto KIMURA
  • Publication number: 20230419011
    Abstract: In an approach to standard cell differentiation using topology and transistor attributes, a first circuit representation of an unidentified cell is received. The first circuit representation of the unidentified cell is converted to a first graph. A second circuit representation of each of one or more golden reference cells are retrieved. The second circuit representation of each of the one or more golden reference cells are converted to one or more second graphs. The first graph is matched to each of the one or more second graphs. One or more match results are reported based on the matching of the first graph to each of the one or more second graphs.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 28, 2023
    Inventors: Timothy A. MCDONLEY, Josh DELOZIER, Benjamin HAYDEN, Kurtis WICKEY
  • Publication number: 20230044517
    Abstract: The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 9, 2023
    Inventors: Timothy A. McDonley, Andrew Elliott, Adam Kimura, Katie T. Liszewski, Thomas Kent, Josh Delozier, Benjamin Hayden